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liverpool: implement Rewind and IndirectBuffer packets

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Daniel R. 2024-12-11 19:40:45 +01:00
parent 51bf98a7b5
commit 2a953391ef
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2 changed files with 48 additions and 0 deletions
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35
src/video_core/amdgpu/liverpool.cpp
View file

@ -610,6 +610,17 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
// const auto* acquire_mem = reinterpret_cast<PM4CmdAcquireMem*>(header); // const auto* acquire_mem = reinterpret_cast<PM4CmdAcquireMem*>(header);
break; break;
} }
case PM4ItOpcode::Rewind: {
const PM4CmdRewind* rewind = reinterpret_cast<const PM4CmdRewind*>(header);
while (!rewind->Valid()) {
mapped_queues[GfxQueueId].cs_state = regs.cs_program;
TracyFiberLeave;
co_yield {};
TracyFiberEnter(dcb_task_name);
regs.cs_program = mapped_queues[GfxQueueId].cs_state;
}
break;
}
case PM4ItOpcode::WaitRegMem: { case PM4ItOpcode::WaitRegMem: {
const auto* wait_reg_mem = reinterpret_cast<const PM4CmdWaitRegMem*>(header); const auto* wait_reg_mem = reinterpret_cast<const PM4CmdWaitRegMem*>(header);
// ASSERT(wait_reg_mem->engine.Value() == PM4CmdWaitRegMem::Engine::Me); // ASSERT(wait_reg_mem->engine.Value() == PM4CmdWaitRegMem::Engine::Me);
@ -630,6 +641,19 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
} }
break; break;
} }
case PM4ItOpcode::IndirectBuffer: {
const auto* indirect_buffer = reinterpret_cast<const PM4CmdIndirectBuffer*>(header);
auto task = ProcessGraphics(
{indirect_buffer->Address<const u32>(), indirect_buffer->ib_size}, {});
while (!task.handle.done()) {
task.handle.resume();
TracyFiberLeave;
co_yield {};
TracyFiberEnter(dcb_task_name);
};
break;
}
case PM4ItOpcode::IncrementDeCounter: { case PM4ItOpcode::IncrementDeCounter: {
++cblock.de_count; ++cblock.de_count;
break; break;
@ -730,6 +754,17 @@ Liverpool::Task Liverpool::ProcessCompute(std::span<const u32> acb, int vqid) {
case PM4ItOpcode::AcquireMem: { case PM4ItOpcode::AcquireMem: {
break; break;
} }
case PM4ItOpcode::Rewind: {
const PM4CmdRewind* rewind = reinterpret_cast<const PM4CmdRewind*>(header);
while (!rewind->Valid()) {
mapped_queues[vqid].cs_state = regs.cs_program;
TracyFiberLeave;
co_yield {};
TracyFiberEnter(acb_task_name);
regs.cs_program = mapped_queues[vqid].cs_state;
}
break;
}
case PM4ItOpcode::SetShReg: { case PM4ItOpcode::SetShReg: {
const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header); const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
std::memcpy(&regs.reg_array[ShRegWordOffset + set_data->reg_offset], header + 2, std::memcpy(&regs.reg_array[ShRegWordOffset + set_data->reg_offset], header + 2,

13
src/video_core/amdgpu/pm4_cmds.h
View file

@ -418,6 +418,19 @@ struct PM4DmaData {
} }
}; };
struct PM4CmdRewind {
PM4Type3Header header;
union {
u32 raw;
BitField<24, 1, u32> offload_enable; ///< Enable offload polling valid bit to IQ
BitField<31, 1, u32> valid; ///< Set when subsequent packets are valid
};
bool Valid() const {
return valid;
}
};
struct PM4CmdWaitRegMem { struct PM4CmdWaitRegMem {
enum class Engine : u32 { Me = 0u, Pfp = 1u }; enum class Engine : u32 { Me = 0u, Pfp = 1u };
enum class MemSpace : u32 { Register = 0u, Memory = 1u }; enum class MemSpace : u32 { Register = 0u, Memory = 1u };