From 2a953391ef9a1ccd0df8b84a9ab365b0c5d2a701 Mon Sep 17 00:00:00 2001
From: "Daniel R." <47796739+polybiusproxy@users.noreply.github.com>
Date: Wed, 11 Dec 2024 19:40:45 +0100
Subject: [PATCH] liverpool: implement Rewind and IndirectBuffer packets

---
 src/video_core/amdgpu/liverpool.cpp | 35 +++++++++++++++++++++++++++++
 src/video_core/amdgpu/pm4_cmds.h    | 13 +++++++++++
 2 files changed, 48 insertions(+)

diff --git a/src/video_core/amdgpu/liverpool.cpp b/src/video_core/amdgpu/liverpool.cpp
index a4eae8e7..8db2d63c 100644
--- a/src/video_core/amdgpu/liverpool.cpp
+++ b/src/video_core/amdgpu/liverpool.cpp
@@ -610,6 +610,17 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
                 // const auto* acquire_mem = reinterpret_cast<PM4CmdAcquireMem*>(header);
                 break;
             }
+            case PM4ItOpcode::Rewind: {
+                const PM4CmdRewind* rewind = reinterpret_cast<const PM4CmdRewind*>(header);
+                while (!rewind->Valid()) {
+                    mapped_queues[GfxQueueId].cs_state = regs.cs_program;
+                    TracyFiberLeave;
+                    co_yield {};
+                    TracyFiberEnter(dcb_task_name);
+                    regs.cs_program = mapped_queues[GfxQueueId].cs_state;
+                }
+                break;
+            }
             case PM4ItOpcode::WaitRegMem: {
                 const auto* wait_reg_mem = reinterpret_cast<const PM4CmdWaitRegMem*>(header);
                 // ASSERT(wait_reg_mem->engine.Value() == PM4CmdWaitRegMem::Engine::Me);
@@ -630,6 +641,19 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
                 }
                 break;
             }
+            case PM4ItOpcode::IndirectBuffer: {
+                const auto* indirect_buffer = reinterpret_cast<const PM4CmdIndirectBuffer*>(header);
+                auto task = ProcessGraphics(
+                    {indirect_buffer->Address<const u32>(), indirect_buffer->ib_size}, {});
+                while (!task.handle.done()) {
+                    task.handle.resume();
+
+                    TracyFiberLeave;
+                    co_yield {};
+                    TracyFiberEnter(dcb_task_name);
+                };
+                break;
+            }
             case PM4ItOpcode::IncrementDeCounter: {
                 ++cblock.de_count;
                 break;
@@ -730,6 +754,17 @@ Liverpool::Task Liverpool::ProcessCompute(std::span<const u32> acb, int vqid) {
         case PM4ItOpcode::AcquireMem: {
             break;
         }
+        case PM4ItOpcode::Rewind: {
+            const PM4CmdRewind* rewind = reinterpret_cast<const PM4CmdRewind*>(header);
+            while (!rewind->Valid()) {
+                mapped_queues[vqid].cs_state = regs.cs_program;
+                TracyFiberLeave;
+                co_yield {};
+                TracyFiberEnter(acb_task_name);
+                regs.cs_program = mapped_queues[vqid].cs_state;
+            }
+            break;
+        }
         case PM4ItOpcode::SetShReg: {
             const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
             std::memcpy(&regs.reg_array[ShRegWordOffset + set_data->reg_offset], header + 2,
diff --git a/src/video_core/amdgpu/pm4_cmds.h b/src/video_core/amdgpu/pm4_cmds.h
index be675128..238e09fa 100644
--- a/src/video_core/amdgpu/pm4_cmds.h
+++ b/src/video_core/amdgpu/pm4_cmds.h
@@ -418,6 +418,19 @@ struct PM4DmaData {
     }
 };
 
+struct PM4CmdRewind {
+    PM4Type3Header header;
+    union {
+        u32 raw;
+        BitField<24, 1, u32> offload_enable; ///< Enable offload polling valid bit to IQ
+        BitField<31, 1, u32> valid;          ///< Set when subsequent packets are valid
+    };
+
+    bool Valid() const {
+        return valid;
+    }
+};
+
 struct PM4CmdWaitRegMem {
     enum class Engine : u32 { Me = 0u, Pfp = 1u };
     enum class MemSpace : u32 { Register = 0u, Memory = 1u };