mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-01-18 12:38:27 +00:00
1ca13870eb
* shader_recompiler: handle fetch shader address offsets parse index & offset sgpr from fetch shader and propagate them to vkBindVertexBuffers * shader_recompiler: fix fetch_shader when offset is not present * video_core: propagate index/offset SGPRs to vkCmdDraw instead of offsetting the buffer address * video_core: add vertex_offset to non-indexed draw calls renamed fetch offset fields
250 lines
6.2 KiB
C++
250 lines
6.2 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include <span>
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#include <boost/container/static_vector.hpp>
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#include "common/assert.h"
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#include "common/types.h"
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#include "shader_recompiler/ir/attribute.h"
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#include "shader_recompiler/ir/reg.h"
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#include "shader_recompiler/ir/type.h"
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#include "video_core/amdgpu/resource.h"
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namespace Shader {
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static constexpr size_t NumUserDataRegs = 16;
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enum class Stage : u32 {
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Fragment,
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Vertex,
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Geometry,
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Export,
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Hull,
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Local,
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Compute,
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};
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constexpr u32 MaxStageTypes = 6;
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[[nodiscard]] constexpr Stage StageFromIndex(size_t index) noexcept {
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return static_cast<Stage>(static_cast<size_t>(Stage::Vertex) + index);
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}
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enum class TextureType : u32 {
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Color1D,
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ColorArray1D,
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Color2D,
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ColorArray2D,
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Color3D,
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ColorCube,
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Buffer,
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};
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constexpr u32 NUM_TEXTURE_TYPES = 7;
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enum class VsOutput : u32 {
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None,
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PointSprite,
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EdgeFlag,
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KillFlag,
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GsCutFlag,
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GsMrtIndex,
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GsVpIndex,
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CullDist0,
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CullDist1,
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CullDist2,
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CullDist3,
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CullDist4,
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CullDist5,
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CullDist6,
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CullDist7,
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ClipDist0,
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ClipDist1,
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ClipDist2,
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ClipDist3,
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ClipDist4,
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ClipDist5,
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ClipDist6,
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ClipDist7,
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};
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using VsOutputMap = std::array<VsOutput, 4>;
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struct Info;
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struct BufferResource {
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u32 sgpr_base;
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u32 dword_offset;
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u32 length;
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IR::Type used_types;
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AmdGpu::Buffer inline_cbuf;
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AmdGpu::DataFormat dfmt;
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AmdGpu::NumberFormat nfmt;
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bool is_storage{};
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bool is_instance_data{};
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bool is_written{};
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constexpr AmdGpu::Buffer GetVsharp(const Info& info) const noexcept;
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};
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using BufferResourceList = boost::container::static_vector<BufferResource, 16>;
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struct ImageResource {
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u32 sgpr_base;
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u32 dword_offset;
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AmdGpu::ImageType type;
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AmdGpu::NumberFormat nfmt;
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bool is_storage;
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bool is_depth;
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};
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using ImageResourceList = boost::container::static_vector<ImageResource, 16>;
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struct SamplerResource {
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u32 sgpr_base;
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u32 dword_offset;
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AmdGpu::Sampler inline_sampler{};
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u32 associated_image : 4;
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u32 disable_aniso : 1;
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constexpr AmdGpu::Sampler GetSsharp(const Info& info) const noexcept;
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};
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using SamplerResourceList = boost::container::static_vector<SamplerResource, 16>;
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struct PushData {
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static constexpr size_t BufOffsetIndex = 2;
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u32 step0;
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u32 step1;
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std::array<u8, 32> buf_offsets;
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void AddOffset(u32 binding, u32 offset) {
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ASSERT(offset < 256 && binding < buf_offsets.size());
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buf_offsets[binding] = offset;
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}
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};
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struct Info {
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struct VsInput {
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enum InstanceIdType : u8 {
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None = 0,
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OverStepRate0 = 1,
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OverStepRate1 = 2,
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Plain = 3,
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};
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AmdGpu::NumberFormat fmt;
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u16 binding;
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u16 num_components;
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u8 sgpr_base;
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u8 dword_offset;
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InstanceIdType instance_step_rate;
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s32 instance_data_buf;
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};
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boost::container::static_vector<VsInput, 32> vs_inputs{};
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struct PsInput {
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u32 param_index;
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bool is_default;
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bool is_flat;
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u32 default_value;
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};
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boost::container::static_vector<PsInput, 32> ps_inputs{};
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struct AttributeFlags {
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bool Get(IR::Attribute attrib, u32 comp = 0) const {
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return flags[Index(attrib)] & (1 << comp);
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}
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bool GetAny(IR::Attribute attrib) const {
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return flags[Index(attrib)];
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}
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void Set(IR::Attribute attrib, u32 comp = 0) {
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flags[Index(attrib)] |= (1 << comp);
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}
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u32 NumComponents(IR::Attribute attrib) const {
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return 4;
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}
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static size_t Index(IR::Attribute attrib) {
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return static_cast<size_t>(attrib);
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}
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std::array<u8, IR::NumAttributes> flags;
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};
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AttributeFlags loads{};
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AttributeFlags stores{};
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boost::container::static_vector<VsOutputMap, 3> vs_outputs;
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s8 vertex_offset_sgpr = -1;
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s8 instance_offset_sgpr = -1;
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BufferResourceList buffers;
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ImageResourceList images;
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SamplerResourceList samplers;
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std::array<u32, 3> workgroup_size{};
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std::array<bool, 3> tgid_enable;
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u32 num_user_data;
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u32 num_input_vgprs;
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std::span<const u32> user_data;
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Stage stage;
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uintptr_t pgm_base{};
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u64 pgm_hash{};
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u32 shared_memory_size{};
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bool has_storage_images{};
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bool has_discard{};
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bool has_image_gather{};
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bool has_image_query{};
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bool uses_group_quad{};
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bool uses_shared{};
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bool uses_fp16{};
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bool uses_step_rates{};
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bool translation_failed{}; // indicates that shader has unsupported instructions
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template <typename T>
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T ReadUd(u32 ptr_index, u32 dword_offset) const noexcept {
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T data;
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const u32* base = user_data.data();
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if (ptr_index != IR::NumScalarRegs) {
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std::memcpy(&base, &user_data[ptr_index], sizeof(base));
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}
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std::memcpy(&data, base + dword_offset, sizeof(T));
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return data;
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}
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[[nodiscard]] std::pair<u32, u32> GetDrawOffsets() const noexcept {
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u32 vertex_offset = 0;
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u32 instance_offset = 0;
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if (vertex_offset_sgpr != -1) {
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vertex_offset = user_data[vertex_offset_sgpr];
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}
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if (instance_offset_sgpr != -1) {
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instance_offset = user_data[instance_offset_sgpr];
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}
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return {vertex_offset, instance_offset};
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}
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};
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constexpr AmdGpu::Buffer BufferResource::GetVsharp(const Info& info) const noexcept {
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return inline_cbuf ? inline_cbuf : info.ReadUd<AmdGpu::Buffer>(sgpr_base, dword_offset);
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}
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constexpr AmdGpu::Sampler SamplerResource::GetSsharp(const Info& info) const noexcept {
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return inline_sampler ? inline_sampler : info.ReadUd<AmdGpu::Sampler>(sgpr_base, dword_offset);
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}
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} // namespace Shader
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template <>
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struct fmt::formatter<Shader::Stage> {
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constexpr auto parse(format_parse_context& ctx) {
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return ctx.begin();
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}
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auto format(const Shader::Stage stage, format_context& ctx) const {
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constexpr static std::array names = {"fs", "vs", "gs", "es", "hs", "ls", "cs"};
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return fmt::format_to(ctx.out(), "{}", names[static_cast<size_t>(stage)]);
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}
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};
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