shader: Add some instructions

This commit is contained in:
IndecisiveTurtle 2024-09-20 01:11:51 +03:00
parent 94d8fea215
commit fdd699a725
3 changed files with 17 additions and 0 deletions
src/shader_recompiler/frontend/translate

View file

@ -506,6 +506,8 @@ void Translator::S_NOT_B64(const GcnInst& inst) {
return ir.GetExec(); return ir.GetExec();
case OperandField::ScalarGPR: case OperandField::ScalarGPR:
return ir.GetThreadBitScalarReg(IR::ScalarReg(operand.code)); return ir.GetThreadBitScalarReg(IR::ScalarReg(operand.code));
case OperandField::ConstZero:
return ir.Imm1(false);
default: default:
UNREACHABLE(); UNREACHABLE();
} }
@ -520,6 +522,9 @@ void Translator::S_NOT_B64(const GcnInst& inst) {
case OperandField::ScalarGPR: case OperandField::ScalarGPR:
ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[0].code), result); ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[0].code), result);
break; break;
case OperandField::ExecLo:
ir.SetExec(result);
break;
default: default:
UNREACHABLE(); UNREACHABLE();
} }

View file

@ -155,6 +155,7 @@ public:
void V_SUBREV_I32(const GcnInst& inst); void V_SUBREV_I32(const GcnInst& inst);
void V_ADDC_U32(const GcnInst& inst); void V_ADDC_U32(const GcnInst& inst);
void V_LDEXP_F32(const GcnInst& inst); void V_LDEXP_F32(const GcnInst& inst);
void V_CVT_PKNORM_U16_F32(const GcnInst& inst);
void V_CVT_PKRTZ_F16_F32(const GcnInst& inst); void V_CVT_PKRTZ_F16_F32(const GcnInst& inst);
// VOP1 // VOP1

View file

@ -89,6 +89,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
return V_ADDC_U32(inst); return V_ADDC_U32(inst);
case Opcode::V_LDEXP_F32: case Opcode::V_LDEXP_F32:
return V_LDEXP_F32(inst); return V_LDEXP_F32(inst);
case Opcode::V_CVT_PKNORM_U16_F32:
return V_CVT_PKNORM_U16_F32(inst);
case Opcode::V_CVT_PKRTZ_F16_F32: case Opcode::V_CVT_PKRTZ_F16_F32:
return V_CVT_PKRTZ_F16_F32(inst); return V_CVT_PKRTZ_F16_F32(inst);
@ -585,6 +587,15 @@ void Translator::V_LDEXP_F32(const GcnInst& inst) {
SetDst(inst.dst[0], ir.FPLdexp(src0, src1)); SetDst(inst.dst[0], ir.FPLdexp(src0, src1));
} }
void Translator::V_CVT_PKNORM_U16_F32(const GcnInst& inst) {
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
const IR::U32 dst0 = ir.ConvertFToU(32, ir.FPMul(src0, ir.Imm32(65535.f)));
const IR::U32 dst1 = ir.ConvertFToU(32, ir.FPMul(src1, ir.Imm32(65535.f)));
const IR::VectorReg dst_reg{inst.dst[0].code};
ir.SetVectorReg(dst_reg, ir.BitFieldInsert(dst0, dst1, ir.Imm32(16), ir.Imm32(16)));
}
void Translator::V_CVT_PKRTZ_F16_F32(const GcnInst& inst) { void Translator::V_CVT_PKRTZ_F16_F32(const GcnInst& inst) {
const IR::Value vec_f32 = const IR::Value vec_f32 =
ir.CompositeConstruct(GetSrc<IR::F32>(inst.src[0]), GetSrc<IR::F32>(inst.src[1])); ir.CompositeConstruct(GetSrc<IR::F32>(inst.src[0]), GetSrc<IR::F32>(inst.src[1]));