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https://github.com/shadps4-emu/shadPS4.git
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Implement IMAGE_STORE_MIP
Not sure if this is the right way to do this, let me know if this needs changing.
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21808240d6
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@ -220,7 +220,7 @@ public:
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void IMAGE_GET_RESINFO(const GcnInst& inst);
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void IMAGE_SAMPLE(const GcnInst& inst);
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void IMAGE_GATHER(const GcnInst& inst);
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void IMAGE_STORE(const GcnInst& inst);
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void IMAGE_STORE(bool has_mip, const GcnInst& inst);
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void IMAGE_LOAD(bool has_mip, const GcnInst& inst);
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void IMAGE_GET_LOD(const GcnInst& inst);
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void IMAGE_ATOMIC(AtomicOp op, const GcnInst& inst);
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@ -47,8 +47,10 @@ void Translator::EmitVectorMemory(const GcnInst& inst) {
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return IMAGE_ATOMIC(AtomicOp::Dec, inst);
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case Opcode::IMAGE_GET_LOD:
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return IMAGE_GET_LOD(inst);
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case Opcode::IMAGE_STORE_MIP:
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return IMAGE_STORE(true, inst);
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case Opcode::IMAGE_STORE:
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return IMAGE_STORE(inst);
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return IMAGE_STORE(false, inst);
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case Opcode::IMAGE_LOAD_MIP:
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return IMAGE_LOAD(true, inst);
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case Opcode::IMAGE_LOAD:
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@ -330,7 +332,7 @@ void Translator::IMAGE_LOAD(bool has_mip, const GcnInst& inst) {
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}
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}
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void Translator::IMAGE_STORE(const GcnInst& inst) {
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void Translator::IMAGE_STORE(bool has_mip, const GcnInst& inst) {
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const auto& mimg = inst.control.mimg;
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IR::VectorReg addr_reg{inst.src[0].code};
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IR::VectorReg data_reg{inst.dst[0].code};
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@ -341,6 +343,9 @@ void Translator::IMAGE_STORE(const GcnInst& inst) {
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ir.CompositeConstruct(ir.GetVectorReg(addr_reg), ir.GetVectorReg(addr_reg + 1),
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ir.GetVectorReg(addr_reg + 2), ir.GetVectorReg(addr_reg + 3));
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IR::TextureInstInfo info{};
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info.explicit_lod.Assign(has_mip);
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boost::container::static_vector<IR::F32, 4> comps;
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for (u32 i = 0; i < 4; i++) {
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if (((mimg.dmask >> i) & 1) == 0) {
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@ -350,7 +355,7 @@ void Translator::IMAGE_STORE(const GcnInst& inst) {
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comps.push_back(ir.GetVectorReg<IR::F32>(data_reg++));
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}
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const IR::Value value = ir.CompositeConstruct(comps[0], comps[1], comps[2], comps[3]);
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ir.ImageWrite(handle, body, value, {});
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ir.ImageWrite(handle, body, value, info);
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}
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void Translator::BUFFER_LOAD(u32 num_dwords, bool is_typed, const GcnInst& inst) {
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