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shader_recompiler: Exclude non-float results from output modifiers. (#1016)

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squidbus 2024-09-22 05:03:17 -07:00 committed by GitHub
parent 8811cc5cc6
commit a18419dd73
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GPG key ID: B5690EEEBB952194
2 changed files with 9 additions and 7 deletions
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13
src/shader_recompiler/frontend/translate/translate.cpp
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@ -281,12 +281,15 @@ template IR::F64 Translator::GetSrc64<IR::F64>(const InstOperand&);
void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
IR::U32F32 result = value;
if (operand.output_modifier.multiplier != 0.f) {
result = ir.FPMul(result, ir.Imm32(operand.output_modifier.multiplier));
}
if (operand.output_modifier.clamp) {
result = ir.FPSaturate(value);
if (value.Type() == IR::Type::F32) {
if (operand.output_modifier.multiplier != 0.f) {
result = ir.FPMul(result, ir.Imm32(operand.output_modifier.multiplier));
}
if (operand.output_modifier.clamp) {
result = ir.FPSaturate(value);
}
}
switch (operand.field) {
case OperandField::ScalarGPR:
return ir.SetScalarReg(IR::ScalarReg(operand.code), result);

3
src/shader_recompiler/frontend/translate/vector_alu.cpp
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@ -569,8 +569,7 @@ void Translator::V_ADDC_U32(const GcnInst& inst) {
const IR::U32 scarry = IR::U32{ir.Select(carry, ir.Imm32(1), ir.Imm32(0))};
const IR::U32 result = ir.IAdd(ir.IAdd(src0, src1), scarry);
const IR::VectorReg dst_reg{inst.dst[0].code};
ir.SetVectorReg(dst_reg, result);
SetDst(inst.dst[0], result);
const IR::U1 less_src0 = ir.ILessThan(result, src0, false);
const IR::U1 less_src1 = ir.ILessThan(result, src1, false);