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Fix some compiler problems with ds3 (#1793)

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- Implement S_CMOVK_I32
- Handle Isoline abstract patch type
This commit is contained in:
baggins183 2024-12-15 06:30:19 -08:00 committed by GitHub
parent d2ac92481b
commit 9aa1c13c7e
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GPG key ID: B5690EEEBB952194
3 changed files with 19 additions and 13 deletions
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20
src/shader_recompiler/frontend/translate/scalar_alu.cpp
View file

@ -161,8 +161,9 @@ void Translator::EmitSOPK(const GcnInst& inst) {
switch (inst.opcode) { switch (inst.opcode) {
// SOPK // SOPK
case Opcode::S_MOVK_I32: case Opcode::S_MOVK_I32:
return S_MOVK(inst); return S_MOVK(inst, false);
case Opcode::S_CMOVK_I32:
return S_MOVK(inst, true);
case Opcode::S_CMPK_EQ_I32: case Opcode::S_CMPK_EQ_I32:
return S_CMPK(ConditionOp::EQ, true, inst); return S_CMPK(ConditionOp::EQ, true, inst);
case Opcode::S_CMPK_LG_I32: case Opcode::S_CMPK_LG_I32:
@ -458,13 +459,16 @@ void Translator::S_ABSDIFF_I32(const GcnInst& inst) {
// SOPK // SOPK
void Translator::S_MOVK(const GcnInst& inst) { void Translator::S_MOVK(const GcnInst& inst, bool is_conditional) {
const auto simm16 = inst.control.sopk.simm; const s16 simm16 = inst.control.sopk.simm;
if (simm16 & (1 << 15)) { // do the sign extension
// TODO: need to verify the case of imm sign extension const s32 simm32 = static_cast<s32>(simm16);
UNREACHABLE(); IR::U32 val = ir.Imm32(simm32);
if (is_conditional) {
// if !SCC its a NOP
val = IR::U32{ir.Select(ir.GetScc(), val, GetSrc(inst.dst[0]))};
} }
SetDst(inst.dst[0], ir.Imm32(simm16)); SetDst(inst.dst[0], val);
} }
void Translator::S_CMPK(ConditionOp cond, bool is_signed, const GcnInst& inst) { void Translator::S_CMPK(ConditionOp cond, bool is_signed, const GcnInst& inst) {

2
src/shader_recompiler/frontend/translate/translate.h
View file

@ -100,7 +100,7 @@ public:
void S_NOT_B32(const GcnInst& inst); void S_NOT_B32(const GcnInst& inst);
// SOPK // SOPK
void S_MOVK(const GcnInst& inst); void S_MOVK(const GcnInst& inst, bool is_conditional);
void S_CMPK(ConditionOp cond, bool is_signed, const GcnInst& inst); void S_CMPK(ConditionOp cond, bool is_signed, const GcnInst& inst);
void S_ADDK_I32(const GcnInst& inst); void S_ADDK_I32(const GcnInst& inst);
void S_MULK_I32(const GcnInst& inst); void S_MULK_I32(const GcnInst& inst);

10
src/shader_recompiler/ir/passes/hull_shader_transform.cpp
View file

@ -398,8 +398,8 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
// communicated to the driver. // communicated to the driver.
// The layout seems to be implied by the type of the abstract domain. // The layout seems to be implied by the type of the abstract domain.
switch (runtime_info.hs_info.tess_type) { switch (runtime_info.hs_info.tess_type) {
case AmdGpu::TessellationType::Quad: case AmdGpu::TessellationType::Isoline:
ASSERT(gcn_factor_idx < 6); ASSERT(gcn_factor_idx < 2);
return IR::PatchFactor(gcn_factor_idx); return IR::PatchFactor(gcn_factor_idx);
case AmdGpu::TessellationType::Triangle: case AmdGpu::TessellationType::Triangle:
ASSERT(gcn_factor_idx < 4); ASSERT(gcn_factor_idx < 4);
@ -407,9 +407,11 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
return IR::Patch::TessellationLodInteriorU; return IR::Patch::TessellationLodInteriorU;
} }
return IR::PatchFactor(gcn_factor_idx); return IR::PatchFactor(gcn_factor_idx);
case AmdGpu::TessellationType::Quad:
ASSERT(gcn_factor_idx < 6);
return IR::PatchFactor(gcn_factor_idx);
default: default:
// Point domain types haven't been seen so far UNREACHABLE();
UNREACHABLE_MSG("Unhandled tess type");
} }
}; };