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https://github.com/shadps4-emu/shadPS4.git
synced 2024-12-28 02:26:07 +00:00
added 32bpp macro detiler
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This commit is contained in:
parent
39fed1f469
commit
9032525b02
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@ -126,6 +126,7 @@ enum class TilingMode : u32 {
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Display_MacroTiled = 0xAu,
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Display_MacroTiled = 0xAu,
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Texture_MicroTiled = 0xDu,
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Texture_MicroTiled = 0xDu,
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Texture_MacroTiled = 0xEu,
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Texture_MacroTiled = 0xEu,
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Texture_Volume = 0x13u,
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};
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};
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constexpr std::string_view NameOf(TilingMode type) {
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constexpr std::string_view NameOf(TilingMode type) {
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@ -294,9 +295,6 @@ struct Image {
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return tiling_index == 5 ? TilingMode::Texture_MicroTiled
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return tiling_index == 5 ? TilingMode::Texture_MicroTiled
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: TilingMode::Depth_MacroTiled;
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: TilingMode::Depth_MacroTiled;
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}
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}
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if (tiling_index == 0x13) {
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return TilingMode::Texture_MicroTiled;
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}
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return static_cast<TilingMode>(tiling_index);
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return static_cast<TilingMode>(tiling_index);
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}
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}
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@ -7,6 +7,7 @@ set(SHADER_FILES
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detile_m32x1.comp
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detile_m32x1.comp
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detile_m32x2.comp
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detile_m32x2.comp
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detile_m32x4.comp
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detile_m32x4.comp
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detile_macro32x1.comp
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fs_tri.vert
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fs_tri.vert
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post_process.frag
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post_process.frag
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)
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)
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@ -15,6 +15,8 @@ layout(std430, binding = 1) buffer output_buf {
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layout(push_constant) uniform image_info {
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layout(push_constant) uniform image_info {
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uint num_levels;
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uint num_levels;
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uint pitch;
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uint pitch;
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uint height;
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uint depth;
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uint sizes[14];
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uint sizes[14];
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} info;
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} info;
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@ -15,6 +15,8 @@ layout(std430, binding = 1) buffer output_buf {
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layout(push_constant) uniform image_info {
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layout(push_constant) uniform image_info {
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uint num_levels;
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uint num_levels;
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uint pitch;
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uint pitch;
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uint height;
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uint depth;
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uint sizes[14];
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uint sizes[14];
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} info;
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} info;
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@ -15,6 +15,8 @@ layout(std430, binding = 1) buffer output_buf {
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layout(push_constant) uniform image_info {
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layout(push_constant) uniform image_info {
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uint num_levels;
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uint num_levels;
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uint pitch;
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uint pitch;
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uint height;
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uint depth;
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uint sizes[14];
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uint sizes[14];
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} info;
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} info;
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@ -18,6 +18,8 @@ layout(std430, binding = 1) buffer output_buf {
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layout(push_constant) uniform image_info {
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layout(push_constant) uniform image_info {
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uint num_levels;
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uint num_levels;
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uint pitch;
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uint pitch;
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uint height;
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uint depth;
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uint sizes[14];
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uint sizes[14];
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} info;
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} info;
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@ -17,6 +17,8 @@ layout(std430, binding = 1) buffer output_buf {
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layout(push_constant) uniform image_info {
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layout(push_constant) uniform image_info {
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uint num_levels;
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uint num_levels;
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uint pitch;
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uint pitch;
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uint height;
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uint depth;
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uint sizes[14];
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uint sizes[14];
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} info;
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} info;
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91
src/video_core/host_shaders/detile_macro32x1.comp
Normal file
91
src/video_core/host_shaders/detile_macro32x1.comp
Normal file
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@ -0,0 +1,91 @@
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#version 450
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layout (local_size_x = 64, local_size_y = 1, local_size_z = 1) in;
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layout(std430, binding = 0) buffer input_buf {
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uint in_data[];
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};
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layout(std430, binding = 1) buffer output_buf {
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uint out_data[];
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};
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layout(push_constant) uniform image_info {
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uint num_levels;
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uint pitch;
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uint height;
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uint depth;
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uint sizes[14];
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} info;
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// Each LUT is 64 bytes, so should fit into K$ given tiled slices locality
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const uint lut_32bpp[][64] = {
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{
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0x00, 0x01, 0x04, 0x05, 0x40, 0x41, 0x44, 0x45,
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0x02, 0x03, 0x06, 0x07, 0x42, 0x43, 0x46, 0x47,
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0x10, 0x11, 0x14, 0x15, 0x50, 0x51, 0x54, 0x55,
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0x12, 0x13, 0x16, 0x17, 0x52, 0x53, 0x56, 0x57,
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0x80, 0x81, 0x84, 0x85, 0xc0, 0xc1, 0xc4, 0xc5,
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0x82, 0x83, 0x86, 0x87, 0xc2, 0xc3, 0xc6, 0xc7,
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0x90, 0x91, 0x94, 0x95, 0xd0, 0xd1, 0xd4, 0xd5,
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0x92, 0x93, 0x96, 0x97, 0xd2, 0xd3, 0xd6, 0xd7,
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},
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{
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0x08, 0x09, 0x0c, 0x0d, 0x48, 0x49, 0x4c, 0x4d,
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0x0a, 0x0b, 0x0e, 0x0f, 0x4a, 0x4b, 0x4e, 0x4f,
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0x18, 0x19, 0x1c, 0x1d, 0x58, 0x59, 0x5c, 0x5d,
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0x1a, 0x1b, 0x1e, 0x1f, 0x5a, 0x5b, 0x5e, 0x5f,
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0x88, 0x89, 0x8c, 0x8d, 0xc8, 0xc9, 0xcc, 0xcd,
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0x8a, 0x8b, 0x8e, 0x8f, 0xca, 0xcb, 0xce, 0xcf,
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0x98, 0x99, 0x9c, 0x9d, 0xd8, 0xd9, 0xdc, 0xdd,
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0x9a, 0x9b, 0x9e, 0x9f, 0xda, 0xdb, 0xde, 0xdf,
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},
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{
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0x20, 0x21, 0x24, 0x25, 0x60, 0x61, 0x64, 0x65,
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0x22, 0x23, 0x26, 0x27, 0x62, 0x63, 0x66, 0x67,
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0x30, 0x31, 0x34, 0x35, 0x70, 0x71, 0x74, 0x75,
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0x32, 0x33, 0x36, 0x37, 0x72, 0x73, 0x76, 0x77,
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0xa0, 0xa1, 0xa4, 0xa5, 0xe0, 0xe1, 0xe4, 0xe5,
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0xa2, 0xa3, 0xa6, 0xa7, 0xe2, 0xe3, 0xe6, 0xe7,
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0xb0, 0xb1, 0xb4, 0xb5, 0xf0, 0xf1, 0xf4, 0xf5,
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0xb2, 0xb3, 0xb6, 0xb7, 0xf2, 0xf3, 0xf6, 0xf7,
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},
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{
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0x28, 0x29, 0x2c, 0x2d, 0x68, 0x69, 0x6c, 0x6d,
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0x2a, 0x2b, 0x2e, 0x2f, 0x6a, 0x6b, 0x6e, 0x6f,
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0x38, 0x39, 0x3c, 0x3d, 0x78, 0x79, 0x7c, 0x7d,
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0x3a, 0x3b, 0x3e, 0x3f, 0x7a, 0x7b, 0x7e, 0x7f,
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0xa8, 0xa9, 0xac, 0xad, 0xe8, 0xe9, 0xec, 0xed,
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0xaa, 0xab, 0xae, 0xaf, 0xea, 0xeb, 0xee, 0xef,
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0xb8, 0xb9, 0xbc, 0xbd, 0xf8, 0xf9, 0xfc, 0xfd,
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0xba, 0xbb, 0xbe, 0xbf, 0xfa, 0xfb, 0xfe, 0xff,
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}
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};
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#define MICRO_TILE_DIM (8)
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#define MICRO_TILE_SZ (1024)
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#define TEXELS_PER_ELEMENT (1)
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#define BPP (32)
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void main() {
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uint x = gl_GlobalInvocationID.x % info.pitch;
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uint y = (gl_GlobalInvocationID.x / info.pitch) % info.height;
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uint z = gl_GlobalInvocationID.x / (info.pitch * info.height);
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uint col = bitfieldExtract(x, 0, 3);
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uint row = bitfieldExtract(y, 0, 3);
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uint lut = bitfieldExtract(z, 0, 2);
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uint idx = lut_32bpp[lut][col + row * MICRO_TILE_DIM];
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uint elem_offs = idx * BPP;
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uint slice_offs = (z / 4) * MICRO_TILE_DIM * MICRO_TILE_DIM * MICRO_TILE_SZ;
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uint tile_row = y / MICRO_TILE_DIM;
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uint tile_column = x / MICRO_TILE_DIM;
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uint tile_offs = ((tile_row * MICRO_TILE_DIM) + tile_column) * MICRO_TILE_SZ;
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uint offs = ((slice_offs + tile_offs) * MICRO_TILE_DIM + elem_offs) / MICRO_TILE_DIM;
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uint p0 = in_data[offs / (BPP / 8)];
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out_data[gl_GlobalInvocationID.x] = p0;
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}
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@ -359,7 +359,10 @@ void ImageInfo::UpdateSize() {
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mip_d = std::bit_ceil(mip_d);
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mip_d = std::bit_ceil(mip_d);
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}
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}
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switch (tiling_mode) {
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auto size_mode_adj =
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tiling_idx == 0x13 ? AmdGpu::TilingMode::Texture_MicroTiled : tiling_mode;
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switch (size_mode_adj) {
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case AmdGpu::TilingMode::Display_Linear: {
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case AmdGpu::TilingMode::Display_Linear: {
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std::tie(mip_info.pitch, mip_info.size) =
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std::tie(mip_info.pitch, mip_info.size) =
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ImageSizeLinearAligned(mip_w, mip_h, bpp, num_samples);
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ImageSizeLinearAligned(mip_w, mip_h, bpp, num_samples);
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@ -12,6 +12,7 @@
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#include "video_core/host_shaders/detile_m32x4_comp.h"
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#include "video_core/host_shaders/detile_m32x4_comp.h"
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#include "video_core/host_shaders/detile_m8x1_comp.h"
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#include "video_core/host_shaders/detile_m8x1_comp.h"
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#include "video_core/host_shaders/detile_m8x2_comp.h"
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#include "video_core/host_shaders/detile_m8x2_comp.h"
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#include "video_core/host_shaders/detile_macro32x1_comp.h"
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#include <boost/container/static_vector.hpp>
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#include <boost/container/static_vector.hpp>
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#include <magic_enum/magic_enum.hpp>
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#include <magic_enum/magic_enum.hpp>
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@ -233,7 +234,8 @@ vk::Format DemoteImageFormatForDetiling(vk::Format format) {
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const DetilerContext* TileManager::GetDetiler(const Image& image) const {
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const DetilerContext* TileManager::GetDetiler(const Image& image) const {
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const auto format = DemoteImageFormatForDetiling(image.info.pixel_format);
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const auto format = DemoteImageFormatForDetiling(image.info.pixel_format);
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if (image.info.tiling_mode == AmdGpu::TilingMode::Texture_MicroTiled) {
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switch (image.info.tiling_mode) {
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case AmdGpu::TilingMode::Texture_MicroTiled:
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switch (format) {
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switch (format) {
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case vk::Format::eR8Uint:
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case vk::Format::eR8Uint:
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return &detilers[DetilerType::Micro8x1];
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return &detilers[DetilerType::Micro8x1];
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@ -248,13 +250,29 @@ const DetilerContext* TileManager::GetDetiler(const Image& image) const {
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default:
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default:
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return nullptr;
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return nullptr;
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}
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}
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case AmdGpu::TilingMode::Texture_Volume:
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switch (format) {
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case vk::Format::eR32Uint:
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if (image.info.size.width % 8 == 0 && image.info.size.height % 8 == 0) {
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return &detilers[DetilerType::Macro32x1];
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} else {
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// Need to test non-tile aligned images
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return nullptr;
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}
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default:
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return nullptr;
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}
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break;
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default:
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return nullptr;
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}
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}
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return nullptr;
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}
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}
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struct DetilerParams {
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struct DetilerParams {
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u32 num_levels;
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u32 num_levels;
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u32 pitch0;
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u32 pitch0;
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u32 height;
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u32 depth;
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u32 sizes[14];
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u32 sizes[14];
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};
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};
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@ -263,7 +281,7 @@ TileManager::TileManager(const Vulkan::Instance& instance, Vulkan::Scheduler& sc
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static const std::array detiler_shaders{
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static const std::array detiler_shaders{
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HostShaders::DETILE_M8X1_COMP, HostShaders::DETILE_M8X2_COMP,
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HostShaders::DETILE_M8X1_COMP, HostShaders::DETILE_M8X2_COMP,
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HostShaders::DETILE_M32X1_COMP, HostShaders::DETILE_M32X2_COMP,
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HostShaders::DETILE_M32X1_COMP, HostShaders::DETILE_M32X2_COMP,
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HostShaders::DETILE_M32X4_COMP,
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HostShaders::DETILE_M32X4_COMP, HostShaders::DETILE_MACRO32X1_COMP,
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};
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};
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boost::container::static_vector<vk::DescriptorSetLayoutBinding, 2> bindings{
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boost::container::static_vector<vk::DescriptorSetLayoutBinding, 2> bindings{
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@ -448,6 +466,8 @@ std::pair<vk::Buffer, u32> TileManager::TryDetile(vk::Buffer in_buffer, u32 in_o
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DetilerParams params;
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DetilerParams params;
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params.pitch0 = image.info.pitch >> (image.info.props.is_block ? 2u : 0u);
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params.pitch0 = image.info.pitch >> (image.info.props.is_block ? 2u : 0u);
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params.height = image.info.size.height;
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params.depth = image.info.size.depth;
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params.num_levels = image.info.resources.levels;
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params.num_levels = image.info.resources.levels;
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ASSERT(image.info.resources.levels <= 14);
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ASSERT(image.info.resources.levels <= 14);
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@ -24,6 +24,8 @@ enum DetilerType : u32 {
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Micro32x2,
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Micro32x2,
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Micro32x4,
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Micro32x4,
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Macro32x1,
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Max
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Max
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};
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};
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