mirrors/shadPS4
1
0
Fork 0
mirror of https://github.com/shadps4-emu/shadPS4.git synced 2025-01-15 11:25:13 +00:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

shader_recompiler: Ignore exec mask for scalar instructions. (#2097)
Some checks are pending
Build and Release / reuse (push) Waiting to run
Details
Build and Release / clang-format (push) Waiting to run
Details
Build and Release / get-info (push) Waiting to run
Details
Build and Release / windows-sdl (push) Blocked by required conditions
Details
Build and Release / windows-qt (push) Blocked by required conditions
Details
Build and Release / macos-sdl (push) Blocked by required conditions
Details
Build and Release / macos-qt (push) Blocked by required conditions
Details
Build and Release / linux-sdl (push) Blocked by required conditions
Details
Build and Release / linux-qt (push) Blocked by required conditions
Details
Build and Release / linux-sdl-gcc (push) Blocked by required conditions
Details
Build and Release / linux-qt-gcc (push) Blocked by required conditions
Details
Build and Release / pre-release (push) Blocked by required conditions
Details

Browse source
This commit is contained in:
squidbus 2025-01-08 09:14:06 -08:00 committed by GitHub
parent 0eee36cbc7
commit 65f9bbbfed
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
1 changed files with 18 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

24
src/shader_recompiler/frontend/control_flow_graph.cpp
View file

@ -47,13 +47,26 @@ static IR::Condition MakeCondition(const GcnInst& inst) {
} }
} }
static bool IgnoresExecMask(Opcode opcode) { static bool IgnoresExecMask(const GcnInst& inst) {
switch (opcode) { // EXEC mask does not affect scalar instructions or branches.
case Opcode::V_WRITELANE_B32: switch (inst.category) {
case InstCategory::ScalarALU:
case InstCategory::ScalarMemory:
case InstCategory::FlowControl:
return true; return true;
default: default:
return false; break;
} }
// Read/Write Lane instructions are not affected either.
switch (inst.opcode) {
case Opcode::V_READLANE_B32:
case Opcode::V_WRITELANE_B32:
case Opcode::V_READFIRSTLANE_B32:
return true;
default:
break;
}
return false;
} }
static constexpr size_t LabelReserveSize = 32; static constexpr size_t LabelReserveSize = 32;
@ -147,8 +160,7 @@ void CFG::EmitDivergenceLabels() {
// If all instructions in the scope ignore exec masking, we shouldn't insert a // If all instructions in the scope ignore exec masking, we shouldn't insert a
// scope. // scope.
const auto start = inst_list.begin() + curr_begin + 1; const auto start = inst_list.begin() + curr_begin + 1;
if (!std::ranges::all_of(start, inst_list.begin() + index, IgnoresExecMask, if (!std::ranges::all_of(start, inst_list.begin() + index, IgnoresExecMask)) {
&GcnInst::opcode)) {
// Add a label to the instruction right after the open scope call. // Add a label to the instruction right after the open scope call.
// It is the start of a new basic block. // It is the start of a new basic block.
const auto& save_inst = inst_list[curr_begin]; const auto& save_inst = inst_list[curr_begin];