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https://github.com/shadps4-emu/shadPS4.git
synced 2025-01-15 11:25:13 +00:00
recompiler: handle reads of output variables in hull shaders (#1962)
* Handle output control point reads in hull shader. Might need additional barriers * output storage class
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parent
da9e45b582
commit
62c47cb1b7
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@ -217,14 +217,6 @@ Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, u32 comp, Id index) {
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const auto pointer{
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ctx.OpAccessChain(component_ptr, ctx.tess_coord, ctx.ConstU32(component))};
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return ctx.OpLoad(ctx.F32[1], pointer);
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} else if (IR::IsParam(attr)) {
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const u32 param_id{u32(attr) - u32(IR::Attribute::Param0)};
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const auto param = ctx.input_params.at(param_id).id;
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const auto param_arr_ptr = ctx.TypePointer(spv::StorageClass::Input, ctx.F32[4]);
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const auto pointer{ctx.OpAccessChain(param_arr_ptr, param, index)};
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const auto position_comp_ptr = ctx.TypePointer(spv::StorageClass::Input, ctx.F32[1]);
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return ctx.OpLoad(ctx.F32[1],
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ctx.OpAccessChain(position_comp_ptr, pointer, ctx.ConstU32(comp)));
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}
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UNREACHABLE();
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}
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@ -351,6 +343,13 @@ Id EmitGetTessGenericAttribute(EmitContext& ctx, Id vertex_index, Id attr_index,
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vertex_index, attr_index, comp_index));
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}
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Id EmitReadTcsGenericOuputAttribute(EmitContext& ctx, Id vertex_index, Id attr_index,
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Id comp_index) {
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const auto attr_comp_ptr = ctx.TypePointer(spv::StorageClass::Output, ctx.F32[1]);
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return ctx.OpLoad(ctx.F32[1], ctx.OpAccessChain(attr_comp_ptr, ctx.output_attr_array,
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vertex_index, attr_index, comp_index));
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}
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void EmitSetTcsGenericAttribute(EmitContext& ctx, Id value, Id attr_index, Id comp_index) {
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// Implied vertex index is invocation_id
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const auto component_ptr = ctx.TypePointer(spv::StorageClass::Output, ctx.F32[1]);
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@ -89,6 +89,8 @@ Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, u32 comp);
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void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value, u32 comp);
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Id EmitGetTessGenericAttribute(EmitContext& ctx, Id vertex_index, Id attr_index, Id comp_index);
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void EmitSetTcsGenericAttribute(EmitContext& ctx, Id value, Id attr_index, Id comp_index);
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Id EmitReadTcsGenericOuputAttribute(EmitContext& ctx, Id vertex_index, Id attr_index,
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Id comp_index);
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Id EmitGetPatch(EmitContext& ctx, IR::Patch patch);
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void EmitSetPatch(EmitContext& ctx, IR::Patch patch, Id value);
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void EmitSetFragColor(EmitContext& ctx, u32 index, u32 component, Id value);
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@ -255,10 +255,6 @@ void Translator::BUFFER_STORE(u32 num_dwords, bool is_typed, const GcnInst& inst
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"Non immediate offset not supported");
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}
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if (info.stage == Stage::Hull) {
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// printf("here\n"); // break
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}
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IR::Value address = [&] -> IR::Value {
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if (is_ring) {
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return ir.CompositeConstruct(ir.GetVectorReg(vaddr), soffset);
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@ -288,6 +288,12 @@ void IREmitter::SetTcsGenericAttribute(const F32& value, const U32& attr_index,
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Inst(Opcode::SetTcsGenericAttribute, value, attr_index, comp_index);
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}
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F32 IREmitter::ReadTcsGenericOuputAttribute(const U32& vertex_index, const U32& attr_index,
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const U32& comp_index) {
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return Inst<F32>(IR::Opcode::ReadTcsGenericOuputAttribute, vertex_index, attr_index,
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comp_index);
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}
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F32 IREmitter::GetPatch(Patch patch) {
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return Inst<F32>(Opcode::GetPatch, patch);
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}
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@ -90,6 +90,9 @@ public:
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const U32& comp_index);
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void SetTcsGenericAttribute(const F32& value, const U32& attr_index, const U32& comp_index);
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[[nodiscard]] F32 ReadTcsGenericOuputAttribute(const U32& vertex_index, const U32& attr_index,
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const U32& comp_index);
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[[nodiscard]] F32 GetPatch(Patch patch);
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void SetPatch(Patch patch, const F32& value);
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@ -64,6 +64,8 @@ OPCODE(GetPatch, F32, Patc
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OPCODE(SetPatch, Void, Patch, F32, )
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OPCODE(GetTessGenericAttribute, F32, U32, U32, U32, )
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OPCODE(SetTcsGenericAttribute, Void, F32, U32, U32, )
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OPCODE(ReadTcsGenericOuputAttribute, F32, U32, U32, U32, )
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// Flags
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OPCODE(GetScc, U1, Void, )
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@ -343,8 +343,8 @@ static IR::U32 TryOptimizeAddressModulo(IR::U32 addr, u32 stride, IR::IREmitter&
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// TODO: can optimize div in control point index similarly to mod
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// Read a TCS input (InputCP region) or TES input (OutputCP region)
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static IR::F32 ReadTessInputComponent(IR::U32 addr, const u32 stride, IR::IREmitter& ir,
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u32 off_dw) {
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static IR::F32 ReadTessControlPointAttribute(IR::U32 addr, const u32 stride, IR::IREmitter& ir,
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u32 off_dw, bool is_output_read_in_tcs) {
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if (off_dw > 0) {
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addr = ir.IAdd(addr, ir.Imm32(off_dw));
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}
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@ -354,7 +354,11 @@ static IR::F32 ReadTessInputComponent(IR::U32 addr, const u32 stride, IR::IREmit
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ir.ShiftRightLogical(ir.IMod(addr_for_attrs, ir.Imm32(stride)), ir.Imm32(4u));
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const IR::U32 comp_index =
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ir.ShiftRightLogical(ir.BitwiseAnd(addr_for_attrs, ir.Imm32(0xFU)), ir.Imm32(2u));
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return ir.GetTessGenericAttribute(control_point_index, attr_index, comp_index);
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if (is_output_read_in_tcs) {
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return ir.ReadTcsGenericOuputAttribute(control_point_index, attr_index, comp_index);
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} else {
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return ir.GetTessGenericAttribute(control_point_index, attr_index, comp_index);
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}
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}
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} // namespace
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@ -481,21 +485,25 @@ void HullShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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case IR::Opcode::LoadSharedU128:
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IR::IREmitter ir{*block, IR::Block::InstructionList::s_iterator_to(inst)};
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const IR::U32 addr{inst.Arg(0)};
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AttributeRegion region = GetAttributeRegionKind(&inst, info, runtime_info);
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const AttributeRegion region = GetAttributeRegionKind(&inst, info, runtime_info);
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const u32 num_dwords = opcode == IR::Opcode::LoadSharedU32
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? 1
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: (opcode == IR::Opcode::LoadSharedU64 ? 2 : 4);
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ASSERT_MSG(region == AttributeRegion::InputCP,
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"Unhandled read of output or patchconst attribute in hull shader");
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ASSERT_MSG(region == AttributeRegion::InputCP ||
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region == AttributeRegion::OutputCP,
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"Unhandled read of patchconst attribute in hull shader");
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const bool is_tcs_output_read = region == AttributeRegion::OutputCP;
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const u32 stride = is_tcs_output_read ? runtime_info.hs_info.hs_output_cp_stride
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: runtime_info.hs_info.ls_stride;
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IR::Value attr_read;
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if (num_dwords == 1) {
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attr_read = ir.BitCast<IR::U32>(
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ReadTessInputComponent(addr, runtime_info.hs_info.ls_stride, ir, 0));
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ReadTessControlPointAttribute(addr, stride, ir, 0, is_tcs_output_read));
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} else {
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boost::container::static_vector<IR::Value, 4> read_components;
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for (auto i = 0; i < num_dwords; i++) {
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const IR::F32 component =
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ReadTessInputComponent(addr, runtime_info.hs_info.ls_stride, ir, i);
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ReadTessControlPointAttribute(addr, stride, ir, i, is_tcs_output_read);
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read_components.push_back(ir.BitCast<IR::U32>(component));
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}
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attr_read = ir.CompositeConstruct(read_components);
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@ -565,8 +573,8 @@ void DomainShaderTransform(IR::Program& program, RuntimeInfo& runtime_info) {
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: (opcode == IR::Opcode::LoadSharedU64 ? 2 : 4);
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const auto GetInput = [&](IR::U32 addr, u32 off_dw) -> IR::F32 {
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if (region == AttributeRegion::OutputCP) {
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return ReadTessInputComponent(
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addr, runtime_info.vs_info.hs_output_cp_stride, ir, off_dw);
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return ReadTessControlPointAttribute(
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addr, runtime_info.vs_info.hs_output_cp_stride, ir, off_dw, false);
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} else {
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ASSERT(region == AttributeRegion::PatchConst);
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return ir.GetPatch(IR::PatchGeneric((addr.U32() >> 2) + off_dw));
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