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https://github.com/shadps4-emu/shadPS4.git
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hot-fix: proper offset calculation for single offset lds instructions
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parent
df8284c5f8
commit
5976300788
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@ -86,7 +86,8 @@ void Translator::V_WRITELANE_B32(const GcnInst& inst) {
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void Translator::DS_ADD_U32(const GcnInst& inst, bool rtn) {
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const IR::U32 addr{GetSrc(inst.src[0])};
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const IR::U32 data{GetSrc(inst.src[1])};
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const IR::U32 offset = ir.Imm32(u32(inst.control.ds.offset0));
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const IR::U32 offset =
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ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0));
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const IR::U32 addr_offset = ir.IAdd(addr, offset);
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const IR::Value original_val = ir.SharedAtomicIAdd(addr_offset, data);
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if (rtn) {
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@ -97,7 +98,8 @@ void Translator::DS_ADD_U32(const GcnInst& inst, bool rtn) {
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void Translator::DS_MIN_U32(const GcnInst& inst, bool is_signed, bool rtn) {
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const IR::U32 addr{GetSrc(inst.src[0])};
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const IR::U32 data{GetSrc(inst.src[1])};
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const IR::U32 offset = ir.Imm32(u32(inst.control.ds.offset0));
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const IR::U32 offset =
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ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0));
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const IR::U32 addr_offset = ir.IAdd(addr, offset);
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const IR::Value original_val = ir.SharedAtomicIMin(addr_offset, data, is_signed);
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if (rtn) {
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@ -108,7 +110,8 @@ void Translator::DS_MIN_U32(const GcnInst& inst, bool is_signed, bool rtn) {
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void Translator::DS_MAX_U32(const GcnInst& inst, bool is_signed, bool rtn) {
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const IR::U32 addr{GetSrc(inst.src[0])};
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const IR::U32 data{GetSrc(inst.src[1])};
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const IR::U32 offset = ir.Imm32(u32(inst.control.ds.offset0));
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const IR::U32 offset =
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ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0));
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const IR::U32 addr_offset = ir.IAdd(addr, offset);
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const IR::Value original_val = ir.SharedAtomicIMax(addr_offset, data, is_signed);
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if (rtn) {
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@ -140,12 +143,14 @@ void Translator::DS_WRITE(int bit_size, bool is_signed, bool is_pair, bool strid
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addr1);
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}
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} else if (bit_size == 64) {
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
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const IR::U32 addr0 = ir.IAdd(
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addr, ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0)));
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const IR::Value data =
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ir.CompositeConstruct(ir.GetVectorReg(data0), ir.GetVectorReg(data0 + 1));
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ir.WriteShared(bit_size, data, addr0);
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} else {
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
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const IR::U32 addr0 = ir.IAdd(
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addr, ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0)));
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ir.WriteShared(bit_size, ir.GetVectorReg(data0), addr0);
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}
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}
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@ -187,26 +192,28 @@ void Translator::DS_READ(int bit_size, bool is_signed, bool is_pair, bool stride
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(data1, 1)});
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}
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} else if (bit_size == 64) {
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
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const IR::U32 addr0 = ir.IAdd(
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addr, ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0)));
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const IR::Value data = ir.LoadShared(bit_size, is_signed, addr0);
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ir.SetVectorReg(dst_reg, IR::U32{ir.CompositeExtract(data, 0)});
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ir.SetVectorReg(dst_reg + 1, IR::U32{ir.CompositeExtract(data, 1)});
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} else {
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
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const IR::U32 addr0 = ir.IAdd(
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addr, ir.Imm32((u32(inst.control.ds.offset1) << 8u) + u32(inst.control.ds.offset0)));
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const IR::U32 data = IR::U32{ir.LoadShared(bit_size, is_signed, addr0)};
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ir.SetVectorReg(dst_reg, data);
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}
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}
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void Translator::DS_APPEND(const GcnInst& inst) {
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const u32 inst_offset = inst.control.ds.offset0;
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const u32 inst_offset = (u32(inst.control.ds.offset1) << 8u) + inst.control.ds.offset0;
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const IR::U32 gds_offset = ir.IAdd(ir.GetM0(), ir.Imm32(inst_offset));
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const IR::U32 prev = ir.DataAppend(gds_offset);
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SetDst(inst.dst[0], prev);
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}
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void Translator::DS_CONSUME(const GcnInst& inst) {
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const u32 inst_offset = inst.control.ds.offset0;
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const u32 inst_offset = (u32(inst.control.ds.offset1) << 8u) + inst.control.ds.offset0;
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const IR::U32 gds_offset = ir.IAdd(ir.GetM0(), ir.Imm32(inst_offset));
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const IR::U32 prev = ir.DataConsume(gds_offset);
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SetDst(inst.dst[0], prev);
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