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vk_graphics_pipeline: Fix regression

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This commit is contained in:
IndecisiveTurtle 2024-08-08 17:00:08 +03:00
parent 341034fc30
commit 3fd2abdd5b
5 changed files with 9 additions and 9 deletions
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8
src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp
View file

@ -129,7 +129,7 @@ Id EmitReadConst(EmitContext& ctx) {
Id EmitReadConstBuffer(EmitContext& ctx, u32 handle, Id index) {
auto& buffer = ctx.buffers[handle];
if (!Sirit::ValidId(buffer.offset)) {
buffer.offset = ctx.GetBufferOffset(handle);
buffer.offset = ctx.GetBufferOffset(buffer.global_binding);
}
const Id offset_dwords{ctx.OpShiftRightLogical(ctx.U32[1], buffer.offset, ctx.ConstU32(2U))};
index = ctx.OpIAdd(ctx.U32[1], index, offset_dwords);
@ -230,7 +230,7 @@ template <u32 N>
static Id EmitLoadBufferF32xN(EmitContext& ctx, u32 handle, Id address) {
auto& buffer = ctx.buffers[handle];
if (!Sirit::ValidId(buffer.offset)) {
buffer.offset = ctx.GetBufferOffset(handle);
buffer.offset = ctx.GetBufferOffset(buffer.global_binding);
}
address = ctx.OpIAdd(ctx.U32[1], address, buffer.offset);
const Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(2u));
@ -412,7 +412,7 @@ template <u32 N>
static Id EmitLoadBufferFormatF32xN(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
auto& buffer = ctx.buffers[handle];
if (!Sirit::ValidId(buffer.offset)) {
buffer.offset = ctx.GetBufferOffset(handle);
buffer.offset = ctx.GetBufferOffset(buffer.global_binding);
}
address = ctx.OpIAdd(ctx.U32[1], address, buffer.offset);
if constexpr (N == 1) {
@ -446,7 +446,7 @@ template <u32 N>
static void EmitStoreBufferF32xN(EmitContext& ctx, u32 handle, Id address, Id value) {
auto& buffer = ctx.buffers[handle];
if (!Sirit::ValidId(buffer.offset)) {
buffer.offset = ctx.GetBufferOffset(handle);
buffer.offset = ctx.GetBufferOffset(buffer.global_binding);
}
address = ctx.OpIAdd(ctx.U32[1], address, buffer.offset);
const Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(2u));

2
src/shader_recompiler/backend/spirv/spirv_emit_context.cpp
View file

@ -352,9 +352,9 @@ void EmitContext::DefineBuffers() {
Decorate(id, spv::Decoration::DescriptorSet, 0U);
Name(id, fmt::format("{}_{}", buffer.is_storage ? "ssbo" : "cbuf", buffer.sgpr_base));
binding++;
buffers.push_back({
.id = id,
.global_binding = binding++,
.data_types = data_types,
.pointer_type = pointer_type,
.buffer = buffer.GetVsharp(info),

1
src/shader_recompiler/backend/spirv/spirv_emit_context.h
View file

@ -203,6 +203,7 @@ public:
struct BufferDefinition {
Id id;
Id offset;
u32 global_binding;
const VectorIds* data_types;
Id pointer_type;
AmdGpu::Buffer buffer;

2
src/video_core/renderer_vulkan/vk_compute_pipeline.cpp
View file

@ -125,7 +125,7 @@ bool ComputePipeline::BindResources(VideoCore::BufferCache& buffer_cache,
const u32 adjust = offset - offset_aligned;
if (adjust != 0) {
ASSERT(adjust % 4 == 0);
push_data.AddOffset(i, adjust);
push_data.AddOffset(binding, adjust);
}
buffer_infos.emplace_back(vk_buffer->Handle(), offset_aligned, size + adjust);
set_writes.push_back({

5
src/video_core/renderer_vulkan/vk_graphics_pipeline.cpp
View file

@ -343,7 +343,7 @@ void GraphicsPipeline::BindResources(const Liverpool::Regs& regs,
push_data.step0 = regs.vgt_instance_step_rate_0;
push_data.step1 = regs.vgt_instance_step_rate_1;
}
for (u32 i = 0; const auto& buffer : stage.buffers) {
for (const auto& buffer : stage.buffers) {
const auto vsharp = buffer.GetVsharp(stage);
if (vsharp) {
const VAddr address = vsharp.base_address;
@ -359,7 +359,7 @@ void GraphicsPipeline::BindResources(const Liverpool::Regs& regs,
const u32 adjust = offset - offset_aligned;
if (adjust != 0) {
ASSERT(adjust % 4 == 0);
push_data.AddOffset(i, adjust);
push_data.AddOffset(binding, adjust);
}
buffer_infos.emplace_back(vk_buffer->Handle(), offset_aligned, size + adjust);
} else {
@ -374,7 +374,6 @@ void GraphicsPipeline::BindResources(const Liverpool::Regs& regs,
: vk::DescriptorType::eUniformBuffer,
.pBufferInfo = &buffer_infos.back(),
});
i++;
}
boost::container::static_vector<AmdGpu::Image, 16> tsharps;