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https://github.com/shadps4-emu/shadPS4.git
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video_core: detiler: display micro 64bpp (#2137)
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8a309c30a9
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394331f206
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@ -119,6 +119,7 @@ constexpr std::string_view NameOf(ImageType type) {
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enum class TilingMode : u32 {
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enum class TilingMode : u32 {
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Depth_MacroTiled = 0u,
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Depth_MacroTiled = 0u,
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Display_Linear = 0x8u,
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Display_Linear = 0x8u,
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Display_MicroTiled = 0x9u,
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Display_MacroTiled = 0xAu,
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Display_MacroTiled = 0xAu,
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Texture_MicroTiled = 0xDu,
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Texture_MicroTiled = 0xDu,
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Texture_MacroTiled = 0xEu,
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Texture_MacroTiled = 0xEu,
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@ -131,6 +132,8 @@ constexpr std::string_view NameOf(TilingMode type) {
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return "Depth_MacroTiled";
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return "Depth_MacroTiled";
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case TilingMode::Display_Linear:
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case TilingMode::Display_Linear:
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return "Display_Linear";
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return "Display_Linear";
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case TilingMode::Display_MicroTiled:
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return "Display_MicroTiled";
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case TilingMode::Display_MacroTiled:
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case TilingMode::Display_MacroTiled:
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return "Display_MacroTiled";
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return "Display_MacroTiled";
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case TilingMode::Texture_MicroTiled:
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case TilingMode::Texture_MicroTiled:
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@ -2,6 +2,7 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# SPDX-License-Identifier: GPL-2.0-or-later
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set(SHADER_FILES
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set(SHADER_FILES
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detilers/display_micro_64bpp.comp
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detilers/macro_32bpp.comp
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detilers/macro_32bpp.comp
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detilers/macro_64bpp.comp
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detilers/macro_64bpp.comp
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detilers/macro_8bpp.comp
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detilers/macro_8bpp.comp
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@ -0,0 +1,60 @@
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#version 450
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layout (local_size_x = 64, local_size_y = 1, local_size_z = 1) in;
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layout(std430, binding = 0) buffer input_buf {
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uint in_data[];
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};
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layout(std430, binding = 1) buffer output_buf {
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uint out_data[];
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};
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layout(push_constant) uniform image_info {
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uint num_levels;
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uint pitch;
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uint height;
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uint c0;
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uint c1;
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} info;
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const uint lut_64bpp[16] = {
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0x05040100, 0x0d0c0908,
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0x07060302, 0x0f0e0b0a,
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0x15141110, 0x1d1c1918,
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0x17161312, 0x1f1e1b1a,
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0x25242120, 0x2d2c2928,
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0x27262322, 0x2f2e2b2a,
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0x35343130, 0x3d3c3938,
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0x37363332, 0x3f3e3b3a,
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};
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#define MICRO_TILE_DIM (8)
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#define MICRO_TILE_SZ (512)
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#define TEXELS_PER_ELEMENT (1)
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#define BPP (64)
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void main() {
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uint x = gl_GlobalInvocationID.x % info.pitch;
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uint y = (gl_GlobalInvocationID.x / info.pitch) % info.height;
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uint z = gl_GlobalInvocationID.x / (info.pitch * info.height);
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uint col = bitfieldExtract(x, 0, 3);
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uint row = bitfieldExtract(y, 0, 3);
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uint idx_dw = lut_64bpp[(col + row * MICRO_TILE_DIM) >> 2u];
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uint byte_ofs = gl_LocalInvocationID.x & 3u;
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uint idx = bitfieldExtract(idx_dw >> (8 * byte_ofs), 0, 8);
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uint slice_offs = z * info.c1 * MICRO_TILE_SZ;
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uint tile_row = y / MICRO_TILE_DIM;
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uint tile_column = x / MICRO_TILE_DIM;
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uint tile_offs = ((tile_row * info.c0) + tile_column) * MICRO_TILE_SZ;
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uint offs = slice_offs + tile_offs + ((idx * BPP) / 8u);
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uint p0 = in_data[(offs >> 2) + 0];
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uint p1 = in_data[(offs >> 2) + 1];
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out_data[2 * gl_GlobalInvocationID.x + 0] = p0;
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out_data[2 * gl_GlobalInvocationID.x + 1] = p1;
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}
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@ -182,6 +182,7 @@ void ImageInfo::UpdateSize() {
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case AmdGpu::TilingMode::Texture_Volume:
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case AmdGpu::TilingMode::Texture_Volume:
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mip_d += (-mip_d) & 3u;
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mip_d += (-mip_d) & 3u;
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[[fallthrough]];
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[[fallthrough]];
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case AmdGpu::TilingMode::Display_MicroTiled:
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case AmdGpu::TilingMode::Texture_MicroTiled: {
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case AmdGpu::TilingMode::Texture_MicroTiled: {
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std::tie(mip_info.pitch, mip_info.size) =
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std::tie(mip_info.pitch, mip_info.size) =
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ImageSizeMicroTiled(mip_w, mip_h, bpp, num_samples);
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ImageSizeMicroTiled(mip_w, mip_h, bpp, num_samples);
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@ -469,9 +469,6 @@ ImageView& TextureCache::FindDepthTarget(BaseDesc& desc) {
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}
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}
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void TextureCache::RefreshImage(Image& image, Vulkan::Scheduler* custom_scheduler /*= nullptr*/) {
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void TextureCache::RefreshImage(Image& image, Vulkan::Scheduler* custom_scheduler /*= nullptr*/) {
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RENDERER_TRACE;
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TRACE_HINT(fmt::format("{:x}:{:x}", image.info.guest_address, image.info.guest_size));
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if (False(image.flags & ImageFlagBits::Dirty)) {
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if (False(image.flags & ImageFlagBits::Dirty)) {
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return;
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return;
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}
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}
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@ -480,6 +477,9 @@ void TextureCache::RefreshImage(Image& image, Vulkan::Scheduler* custom_schedule
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return;
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return;
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}
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}
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RENDERER_TRACE;
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TRACE_HINT(fmt::format("{:x}:{:x}", image.info.guest_address, image.info.guest_size));
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if (True(image.flags & ImageFlagBits::MaybeCpuDirty) &&
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if (True(image.flags & ImageFlagBits::MaybeCpuDirty) &&
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False(image.flags & ImageFlagBits::CpuDirty)) {
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False(image.flags & ImageFlagBits::CpuDirty)) {
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// The image size should be less than page size to be considered MaybeCpuDirty
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// The image size should be less than page size to be considered MaybeCpuDirty
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@ -8,6 +8,7 @@
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#include "video_core/texture_cache/image_view.h"
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#include "video_core/texture_cache/image_view.h"
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#include "video_core/texture_cache/tile_manager.h"
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#include "video_core/texture_cache/tile_manager.h"
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#include "video_core/host_shaders/detilers/display_micro_64bpp_comp.h"
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#include "video_core/host_shaders/detilers/macro_32bpp_comp.h"
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#include "video_core/host_shaders/detilers/macro_32bpp_comp.h"
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#include "video_core/host_shaders/detilers/macro_64bpp_comp.h"
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#include "video_core/host_shaders/detilers/macro_64bpp_comp.h"
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#include "video_core/host_shaders/detilers/macro_8bpp_comp.h"
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#include "video_core/host_shaders/detilers/macro_8bpp_comp.h"
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@ -53,6 +54,14 @@ const DetilerContext* TileManager::GetDetiler(const ImageInfo& info) const {
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return nullptr;
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return nullptr;
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}
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}
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break;
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break;
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case AmdGpu::TilingMode::Display_MicroTiled:
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switch (bpp) {
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case 64:
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return &detilers[DetilerType::Display_Micro64];
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default:
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return nullptr;
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}
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break;
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default:
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default:
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return nullptr;
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return nullptr;
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}
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}
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@ -68,10 +77,11 @@ struct DetilerParams {
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TileManager::TileManager(const Vulkan::Instance& instance, Vulkan::Scheduler& scheduler)
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TileManager::TileManager(const Vulkan::Instance& instance, Vulkan::Scheduler& scheduler)
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: instance{instance}, scheduler{scheduler} {
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: instance{instance}, scheduler{scheduler} {
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static const std::array detiler_shaders{
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static const std::array detiler_shaders{
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HostShaders::MICRO_8BPP_COMP, HostShaders::MICRO_16BPP_COMP,
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HostShaders::MICRO_8BPP_COMP, HostShaders::MICRO_16BPP_COMP,
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HostShaders::MICRO_32BPP_COMP, HostShaders::MICRO_64BPP_COMP,
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HostShaders::MICRO_32BPP_COMP, HostShaders::MICRO_64BPP_COMP,
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HostShaders::MICRO_128BPP_COMP, HostShaders::MACRO_8BPP_COMP,
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HostShaders::MICRO_128BPP_COMP, HostShaders::MACRO_8BPP_COMP,
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HostShaders::MACRO_32BPP_COMP, HostShaders::MACRO_64BPP_COMP,
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HostShaders::MACRO_32BPP_COMP, HostShaders::MACRO_64BPP_COMP,
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HostShaders::DISPLAY_MICRO_64BPP_COMP,
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};
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};
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boost::container::static_vector<vk::DescriptorSetLayoutBinding, 2> bindings{
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boost::container::static_vector<vk::DescriptorSetLayoutBinding, 2> bindings{
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@ -258,7 +268,8 @@ std::pair<vk::Buffer, u32> TileManager::TryDetile(vk::Buffer in_buffer, u32 in_o
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params.num_levels = info.resources.levels;
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params.num_levels = info.resources.levels;
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params.pitch0 = info.pitch >> (info.props.is_block ? 2u : 0u);
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params.pitch0 = info.pitch >> (info.props.is_block ? 2u : 0u);
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params.height = info.size.height;
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params.height = info.size.height;
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if (info.tiling_mode == AmdGpu::TilingMode::Texture_Volume) {
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if (info.tiling_mode == AmdGpu::TilingMode::Texture_Volume ||
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info.tiling_mode == AmdGpu::TilingMode::Display_MicroTiled) {
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ASSERT(info.resources.levels == 1);
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ASSERT(info.resources.levels == 1);
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const auto tiles_per_row = info.pitch / 8u;
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const auto tiles_per_row = info.pitch / 8u;
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const auto tiles_per_slice = tiles_per_row * ((info.size.height + 7u) / 8u);
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const auto tiles_per_slice = tiles_per_row * ((info.size.height + 7u) / 8u);
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@ -22,6 +22,8 @@ enum DetilerType : u32 {
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Macro32,
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Macro32,
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Macro64,
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Macro64,
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Display_Micro64,
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Max
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Max
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};
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};
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