mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2024-12-28 02:26:07 +00:00
video_core: fix for targets clears and copies (#1670)
This commit is contained in:
parent
15ae7a094d
commit
37f4bad2b7
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@ -102,9 +102,6 @@ RenderState Rasterizer::PrepareRenderState(u32 mrt_mask) {
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continue;
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continue;
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}
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}
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const bool is_clear = texture_cache.IsMetaCleared(col_buf.CmaskAddress());
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texture_cache.TouchMeta(col_buf.CmaskAddress(), false);
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const auto& hint = liverpool->last_cb_extent[col_buf_id];
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const auto& hint = liverpool->last_cb_extent[col_buf_id];
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auto& [image_id, desc] = cb_descs.emplace_back(std::piecewise_construct, std::tuple{},
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auto& [image_id, desc] = cb_descs.emplace_back(std::piecewise_construct, std::tuple{},
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std::tuple{col_buf, hint});
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std::tuple{col_buf, hint});
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@ -113,6 +110,10 @@ RenderState Rasterizer::PrepareRenderState(u32 mrt_mask) {
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auto& image = texture_cache.GetImage(image_id);
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auto& image = texture_cache.GetImage(image_id);
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image.binding.is_target = 1u;
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image.binding.is_target = 1u;
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const auto slice = image_view.info.range.base.layer;
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const bool is_clear = texture_cache.IsMetaCleared(col_buf.CmaskAddress(), slice);
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texture_cache.TouchMeta(col_buf.CmaskAddress(), slice, false);
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const auto mip = image_view.info.range.base.level;
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const auto mip = image_view.info.range.base.level;
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state.width = std::min<u32>(state.width, std::max(image.info.size.width >> mip, 1u));
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state.width = std::min<u32>(state.width, std::max(image.info.size.width >> mip, 1u));
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state.height = std::min<u32>(state.height, std::max(image.info.size.height >> mip, 1u));
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state.height = std::min<u32>(state.height, std::max(image.info.size.height >> mip, 1u));
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@ -134,8 +135,6 @@ RenderState Rasterizer::PrepareRenderState(u32 mrt_mask) {
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(regs.depth_control.stencil_enable &&
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(regs.depth_control.stencil_enable &&
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regs.depth_buffer.stencil_info.format != StencilFormat::Invalid))) {
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regs.depth_buffer.stencil_info.format != StencilFormat::Invalid))) {
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const auto htile_address = regs.depth_htile_data_base.GetAddress();
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const auto htile_address = regs.depth_htile_data_base.GetAddress();
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const bool is_clear = regs.depth_render_control.depth_clear_enable ||
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texture_cache.IsMetaCleared(htile_address);
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const auto& hint = liverpool->last_db_extent;
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const auto& hint = liverpool->last_db_extent;
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auto& [image_id, desc] =
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auto& [image_id, desc] =
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db_desc.emplace(std::piecewise_construct, std::tuple{},
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db_desc.emplace(std::piecewise_construct, std::tuple{},
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@ -146,6 +145,11 @@ RenderState Rasterizer::PrepareRenderState(u32 mrt_mask) {
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auto& image = texture_cache.GetImage(image_id);
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auto& image = texture_cache.GetImage(image_id);
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image.binding.is_target = 1u;
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image.binding.is_target = 1u;
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const auto slice = image_view.info.range.base.layer;
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const bool is_clear = regs.depth_render_control.depth_clear_enable ||
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texture_cache.IsMetaCleared(htile_address, slice);
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ASSERT(desc.view_info.range.extent.layers == 1);
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state.width = std::min<u32>(state.width, image.info.size.width);
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state.width = std::min<u32>(state.width, image.info.size.width);
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state.height = std::min<u32>(state.height, image.info.size.height);
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state.height = std::min<u32>(state.height, image.info.size.height);
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state.depth_image = image.image;
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state.depth_image = image.image;
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@ -157,7 +161,7 @@ RenderState Rasterizer::PrepareRenderState(u32 mrt_mask) {
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.clearValue = vk::ClearValue{.depthStencil = {.depth = regs.depth_clear,
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.clearValue = vk::ClearValue{.depthStencil = {.depth = regs.depth_clear,
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.stencil = regs.stencil_clear}},
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.stencil = regs.stencil_clear}},
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};
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};
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texture_cache.TouchMeta(htile_address, false);
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texture_cache.TouchMeta(htile_address, slice, false);
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state.has_depth =
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state.has_depth =
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regs.depth_buffer.z_info.format != AmdGpu::Liverpool::DepthBuffer::ZFormat::Invalid;
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regs.depth_buffer.z_info.format != AmdGpu::Liverpool::DepthBuffer::ZFormat::Invalid;
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state.has_stencil = regs.depth_buffer.stencil_info.format !=
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state.has_stencil = regs.depth_buffer.stencil_info.format !=
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@ -359,9 +363,11 @@ bool Rasterizer::BindResources(const Pipeline* pipeline) {
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// will need its full emulation anyways. For cases of metadata read a warning will be
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// will need its full emulation anyways. For cases of metadata read a warning will be
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// logged.
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// logged.
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const auto IsMetaUpdate = [&](const auto& desc) {
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const auto IsMetaUpdate = [&](const auto& desc) {
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const VAddr address = desc.GetSharp(info).base_address;
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const auto sharp = desc.GetSharp(info);
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const VAddr address = sharp.base_address;
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if (desc.is_written) {
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if (desc.is_written) {
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if (texture_cache.TouchMeta(address, true)) {
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// Assume all slices were updates
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if (texture_cache.ClearMeta(address)) {
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LOG_TRACE(Render_Vulkan, "Metadata update skipped");
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LOG_TRACE(Render_Vulkan, "Metadata update skipped");
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return true;
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return true;
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}
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}
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@ -373,17 +379,36 @@ bool Rasterizer::BindResources(const Pipeline* pipeline) {
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return false;
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return false;
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};
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};
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// Assume if a shader reads and writes metas at the same time, it is a copy shader.
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bool meta_read = false;
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for (const auto& desc : info.buffers) {
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for (const auto& desc : info.buffers) {
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if (desc.is_gds_buffer) {
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if (desc.is_gds_buffer) {
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continue;
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continue;
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}
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}
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if (IsMetaUpdate(desc)) {
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if (!desc.is_written) {
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return false;
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const VAddr address = desc.GetSharp(info).base_address;
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meta_read = texture_cache.IsMeta(address);
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}
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}
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}
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}
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for (const auto& desc : info.texture_buffers) {
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for (const auto& desc : info.texture_buffers) {
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if (IsMetaUpdate(desc)) {
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if (!desc.is_written) {
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return false;
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const VAddr address = desc.GetSharp(info).base_address;
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meta_read = texture_cache.IsMeta(address);
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}
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}
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if (!meta_read) {
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for (const auto& desc : info.buffers) {
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if (IsMetaUpdate(desc)) {
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return false;
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}
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}
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for (const auto& desc : info.texture_buffers) {
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if (IsMetaUpdate(desc)) {
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return false;
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}
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}
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}
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}
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}
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}
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}
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@ -398,17 +398,15 @@ ImageView& TextureCache::FindRenderTarget(BaseDesc& desc) {
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// Register meta data for this color buffer
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// Register meta data for this color buffer
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if (!(image.flags & ImageFlagBits::MetaRegistered)) {
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if (!(image.flags & ImageFlagBits::MetaRegistered)) {
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if (desc.info.meta_info.cmask_addr) {
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if (desc.info.meta_info.cmask_addr) {
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surface_metas.emplace(
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surface_metas.emplace(desc.info.meta_info.cmask_addr,
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desc.info.meta_info.cmask_addr,
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MetaDataInfo{.type = MetaDataInfo::Type::CMask});
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MetaDataInfo{.type = MetaDataInfo::Type::CMask, .is_cleared = true});
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image.info.meta_info.cmask_addr = desc.info.meta_info.cmask_addr;
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image.info.meta_info.cmask_addr = desc.info.meta_info.cmask_addr;
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image.flags |= ImageFlagBits::MetaRegistered;
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image.flags |= ImageFlagBits::MetaRegistered;
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}
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}
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if (desc.info.meta_info.fmask_addr) {
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if (desc.info.meta_info.fmask_addr) {
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surface_metas.emplace(
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surface_metas.emplace(desc.info.meta_info.fmask_addr,
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desc.info.meta_info.fmask_addr,
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MetaDataInfo{.type = MetaDataInfo::Type::FMask});
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MetaDataInfo{.type = MetaDataInfo::Type::FMask, .is_cleared = true});
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image.info.meta_info.fmask_addr = desc.info.meta_info.fmask_addr;
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image.info.meta_info.fmask_addr = desc.info.meta_info.fmask_addr;
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image.flags |= ImageFlagBits::MetaRegistered;
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image.flags |= ImageFlagBits::MetaRegistered;
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}
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}
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@ -428,9 +426,8 @@ ImageView& TextureCache::FindDepthTarget(BaseDesc& desc) {
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// Register meta data for this depth buffer
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// Register meta data for this depth buffer
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if (!(image.flags & ImageFlagBits::MetaRegistered)) {
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if (!(image.flags & ImageFlagBits::MetaRegistered)) {
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if (desc.info.meta_info.htile_addr) {
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if (desc.info.meta_info.htile_addr) {
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surface_metas.emplace(
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surface_metas.emplace(desc.info.meta_info.htile_addr,
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desc.info.meta_info.htile_addr,
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MetaDataInfo{.type = MetaDataInfo::Type::HTile});
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MetaDataInfo{.type = MetaDataInfo::Type::HTile, .is_cleared = true});
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image.info.meta_info.htile_addr = desc.info.meta_info.htile_addr;
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image.info.meta_info.htile_addr = desc.info.meta_info.htile_addr;
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image.flags |= ImageFlagBits::MetaRegistered;
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image.flags |= ImageFlagBits::MetaRegistered;
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}
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}
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@ -156,18 +156,31 @@ public:
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return surface_metas.contains(address);
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return surface_metas.contains(address);
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}
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}
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bool IsMetaCleared(VAddr address) const {
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bool IsMetaCleared(VAddr address, u32 slice) const {
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const auto& it = surface_metas.find(address);
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const auto& it = surface_metas.find(address);
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if (it != surface_metas.end()) {
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if (it != surface_metas.end()) {
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return it.value().is_cleared;
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return it.value().clear_mask & (1u << slice);
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}
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}
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return false;
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return false;
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}
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}
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bool TouchMeta(VAddr address, bool is_clear) {
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bool ClearMeta(VAddr address) {
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auto it = surface_metas.find(address);
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auto it = surface_metas.find(address);
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if (it != surface_metas.end()) {
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if (it != surface_metas.end()) {
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it.value().is_cleared = is_clear;
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it.value().clear_mask = u32(-1);
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return true;
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}
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return false;
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}
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bool TouchMeta(VAddr address, u32 slice, bool is_clear) {
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auto it = surface_metas.find(address);
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if (it != surface_metas.end()) {
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if (is_clear) {
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it.value().clear_mask |= 1u << slice;
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} else {
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it.value().clear_mask &= ~(1u << slice);
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}
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return true;
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return true;
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}
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}
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return false;
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return false;
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@ -280,7 +293,7 @@ private:
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HTile,
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HTile,
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};
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};
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Type type;
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Type type;
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bool is_cleared;
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u32 clear_mask{u32(-1)};
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};
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};
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tsl::robin_map<VAddr, MetaDataInfo> surface_metas;
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tsl::robin_map<VAddr, MetaDataInfo> surface_metas;
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};
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};
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