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tile: Fix some tile thickness calculation errors. (#2203)
* tile: Fix some tile thickness calculation errors. * tile: Do not pad mip height to tile height.
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5c62a00134
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@ -178,7 +178,6 @@ void ImageInfo::UpdateSize() {
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case AmdGpu::TilingMode::Display_Linear: {
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std::tie(mip_info.pitch, mip_info.size) =
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ImageSizeLinearAligned(mip_w, mip_h, bpp, num_samples);
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mip_info.height = mip_h;
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break;
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}
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case AmdGpu::TilingMode::Texture_Volume:
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@ -188,12 +187,7 @@ void ImageInfo::UpdateSize() {
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case AmdGpu::TilingMode::Display_MicroTiled:
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case AmdGpu::TilingMode::Texture_MicroTiled: {
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std::tie(mip_info.pitch, mip_info.size) =
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ImageSizeMicroTiled(mip_w, mip_h, bpp, thickness, num_samples);
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mip_info.height = std::max(mip_h, 8u);
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if (props.is_block) {
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mip_info.pitch = std::max(mip_info.pitch * 4, 32u);
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mip_info.height = std::max(mip_info.height * 4, 32u);
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}
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ImageSizeMicroTiled(mip_w, mip_h, thickness, bpp, num_samples);
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break;
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}
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case AmdGpu::TilingMode::Display_MacroTiled:
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@ -208,6 +202,11 @@ void ImageInfo::UpdateSize() {
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UNREACHABLE();
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}
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}
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mip_info.height = mip_h;
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if (props.is_block) {
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mip_info.pitch = std::max(mip_info.pitch * 4, 32u);
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mip_info.height = std::max(mip_info.height * 4, 32u);
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}
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mip_info.size *= mip_d;
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mip_info.offset = guest_size;
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mips_layout.emplace_back(mip_info);
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@ -313,8 +313,8 @@ constexpr std::pair<u32, size_t> ImageSizeMicroTiled(u32 pitch, u32 height, u32
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const auto& [pitch_align, height_align] = micro_tile_extent;
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auto pitch_aligned = (pitch + pitch_align - 1) & ~(pitch_align - 1);
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const auto height_aligned = (height + height_align - 1) & ~(height_align - 1);
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size_t log_sz = (pitch_aligned * height_aligned * bpp * num_samples * thickness + 7) / 8;
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while (log_sz % 256) {
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size_t log_sz = (pitch_aligned * height_aligned * bpp * num_samples + 7) / 8;
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while ((log_sz * thickness) % 256) {
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pitch_aligned += pitch_align;
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log_sz = (pitch_aligned * height_aligned * bpp * num_samples + 7) / 8;
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}
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