mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2024-12-28 18:46:06 +00:00
renderer_vulkan: Various attachment cleanup and fixes. (#1795)
This commit is contained in:
parent
aba2b29074
commit
14dc136832
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@ -428,6 +428,14 @@ struct Liverpool {
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BitField<0, 22, u32> tile_max;
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BitField<0, 22, u32> tile_max;
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} depth_slice;
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} depth_slice;
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bool DepthValid() const {
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return Address() != 0 && z_info.format != ZFormat::Invalid;
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}
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bool StencilValid() const {
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return Address() != 0 && stencil_info.format != StencilFormat::Invalid;
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}
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u32 Pitch() const {
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u32 Pitch() const {
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return (depth_size.pitch_tile_max + 1) << 3;
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return (depth_size.pitch_tile_max + 1) << 3;
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}
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}
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@ -1275,6 +1283,26 @@ struct Liverpool {
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return nullptr;
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return nullptr;
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}
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}
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u32 NumSamples() const {
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// It seems that the number of samples > 1 set in the AA config doesn't mean we're
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// always rendering with MSAA, so we need to derive MS ratio from the CB and DB
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// settings.
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u32 num_samples = 1u;
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if (color_control.mode != ColorControl::OperationMode::Disable) {
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for (auto cb = 0u; cb < NumColorBuffers; ++cb) {
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const auto& col_buf = color_buffers[cb];
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if (!col_buf) {
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continue;
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}
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num_samples = std::max(num_samples, col_buf.NumSamples());
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}
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}
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if (depth_buffer.DepthValid() || depth_buffer.StencilValid()) {
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num_samples = std::max(num_samples, depth_buffer.NumSamples());
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}
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return num_samples;
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}
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void SetDefaults();
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void SetDefaults();
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};
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};
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@ -85,10 +85,6 @@ public:
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return key.mrt_mask;
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return key.mrt_mask;
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}
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}
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bool IsDepthEnabled() const {
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return key.depth_stencil.depth_enable.Value();
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}
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[[nodiscard]] bool IsPrimitiveListTopology() const {
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[[nodiscard]] bool IsPrimitiveListTopology() const {
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return key.prim_type == AmdGpu::PrimitiveType::PointList ||
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return key.prim_type == AmdGpu::PrimitiveType::PointList ||
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key.prim_type == AmdGpu::PrimitiveType::LineList ||
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key.prim_type == AmdGpu::PrimitiveType::LineList ||
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@ -258,32 +258,28 @@ bool PipelineCache::RefreshGraphicsKey() {
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auto& key = graphics_key;
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auto& key = graphics_key;
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key.depth_stencil = regs.depth_control;
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key.depth_stencil = regs.depth_control;
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key.stencil = regs.stencil_control;
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key.depth_stencil.depth_write_enable.Assign(regs.depth_control.depth_write_enable.Value() &&
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key.depth_stencil.depth_write_enable.Assign(regs.depth_control.depth_write_enable.Value() &&
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!regs.depth_render_control.depth_clear_enable);
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!regs.depth_render_control.depth_clear_enable);
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key.depth_bias_enable = regs.polygon_control.NeedsBias();
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key.depth_bias_enable = regs.polygon_control.NeedsBias();
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const auto& db = regs.depth_buffer;
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const auto depth_format = instance.GetSupportedFormat(
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const auto ds_format = instance.GetSupportedFormat(
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LiverpoolToVK::DepthFormat(regs.depth_buffer.z_info.format,
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LiverpoolToVK::DepthFormat(db.z_info.format, db.stencil_info.format),
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regs.depth_buffer.stencil_info.format),
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vk::FormatFeatureFlagBits2::eDepthStencilAttachment);
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vk::FormatFeatureFlagBits2::eDepthStencilAttachment);
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if (db.z_info.format != AmdGpu::Liverpool::DepthBuffer::ZFormat::Invalid) {
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if (regs.depth_buffer.DepthValid()) {
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key.depth_format = ds_format;
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key.depth_format = depth_format;
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} else {
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} else {
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key.depth_format = vk::Format::eUndefined;
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key.depth_format = vk::Format::eUndefined;
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key.depth_stencil.depth_enable.Assign(false);
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}
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}
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if (regs.depth_control.depth_enable) {
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if (regs.depth_buffer.StencilValid()) {
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key.depth_stencil.depth_enable.Assign(key.depth_format != vk::Format::eUndefined);
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key.stencil_format = depth_format;
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}
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key.stencil = regs.stencil_control;
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if (db.stencil_info.format != AmdGpu::Liverpool::DepthBuffer::StencilFormat::Invalid) {
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key.stencil_format = key.depth_format;
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} else {
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} else {
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key.stencil_format = vk::Format::eUndefined;
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key.stencil_format = vk::Format::eUndefined;
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key.depth_stencil.stencil_enable.Assign(false);
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}
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}
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if (key.depth_stencil.stencil_enable) {
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key.depth_stencil.stencil_enable.Assign(key.stencil_format != vk::Format::eUndefined);
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}
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key.prim_type = regs.primitive_type;
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key.prim_type = regs.primitive_type;
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key.enable_primitive_restart = regs.enable_primitive_restart & 1;
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key.enable_primitive_restart = regs.enable_primitive_restart & 1;
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key.primitive_restart_index = regs.primitive_restart_index;
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key.primitive_restart_index = regs.primitive_restart_index;
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@ -291,7 +287,7 @@ bool PipelineCache::RefreshGraphicsKey() {
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key.cull_mode = regs.polygon_control.CullingMode();
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key.cull_mode = regs.polygon_control.CullingMode();
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key.clip_space = regs.clipper_control.clip_space;
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key.clip_space = regs.clipper_control.clip_space;
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key.front_face = regs.polygon_control.front_face;
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key.front_face = regs.polygon_control.front_face;
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key.num_samples = regs.aa_config.NumSamples();
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key.num_samples = regs.NumSamples();
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const bool skip_cb_binding =
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const bool skip_cb_binding =
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regs.color_control.mode == AmdGpu::Liverpool::ColorControl::OperationMode::Disable;
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regs.color_control.mode == AmdGpu::Liverpool::ColorControl::OperationMode::Disable;
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@ -437,8 +433,6 @@ bool PipelineCache::RefreshGraphicsKey() {
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}
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}
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}
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}
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u32 num_samples = 1u;
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// Second pass to fill remain CB pipeline key data
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// Second pass to fill remain CB pipeline key data
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for (auto cb = 0u, remapped_cb = 0u; cb < Liverpool::NumColorBuffers; ++cb) {
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for (auto cb = 0u, remapped_cb = 0u; cb < Liverpool::NumColorBuffers; ++cb) {
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auto const& col_buf = regs.color_buffers[cb];
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auto const& col_buf = regs.color_buffers[cb];
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@ -463,15 +457,8 @@ bool PipelineCache::RefreshGraphicsKey() {
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key.write_masks[remapped_cb] = vk::ColorComponentFlags{regs.color_target_mask.GetMask(cb)};
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key.write_masks[remapped_cb] = vk::ColorComponentFlags{regs.color_target_mask.GetMask(cb)};
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key.cb_shader_mask.SetMask(remapped_cb, regs.color_shader_mask.GetMask(cb));
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key.cb_shader_mask.SetMask(remapped_cb, regs.color_shader_mask.GetMask(cb));
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++remapped_cb;
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++remapped_cb;
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num_samples = std::max(num_samples, 1u << col_buf.attrib.num_samples_log2);
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}
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}
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// It seems that the number of samples > 1 set in the AA config doesn't mean we're always
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// rendering with MSAA, so we need to derive MS ratio from the CB settings.
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num_samples = std::max(num_samples, regs.depth_buffer.NumSamples());
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key.num_samples = num_samples;
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return true;
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return true;
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} // namespace Vulkan
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} // namespace Vulkan
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@ -87,9 +87,11 @@ RenderState Rasterizer::PrepareRenderState(u32 mrt_mask) {
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LOG_WARNING(Render_Vulkan, "Color buffers require gamma correction");
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LOG_WARNING(Render_Vulkan, "Color buffers require gamma correction");
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}
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}
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const bool skip_cb_binding =
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regs.color_control.mode == AmdGpu::Liverpool::ColorControl::OperationMode::Disable;
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for (auto col_buf_id = 0u; col_buf_id < Liverpool::NumColorBuffers; ++col_buf_id) {
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for (auto col_buf_id = 0u; col_buf_id < Liverpool::NumColorBuffers; ++col_buf_id) {
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const auto& col_buf = regs.color_buffers[col_buf_id];
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const auto& col_buf = regs.color_buffers[col_buf_id];
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if (!col_buf) {
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if (skip_cb_binding || !col_buf) {
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continue;
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continue;
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}
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}
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@ -134,12 +136,8 @@ RenderState Rasterizer::PrepareRenderState(u32 mrt_mask) {
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};
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};
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}
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}
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using ZFormat = AmdGpu::Liverpool::DepthBuffer::ZFormat;
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if ((regs.depth_control.depth_enable && regs.depth_buffer.DepthValid()) ||
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using StencilFormat = AmdGpu::Liverpool::DepthBuffer::StencilFormat;
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(regs.depth_control.stencil_enable && regs.depth_buffer.StencilValid())) {
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if (regs.depth_buffer.Address() != 0 &&
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((regs.depth_control.depth_enable && regs.depth_buffer.z_info.format != ZFormat::Invalid) ||
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(regs.depth_control.stencil_enable &&
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regs.depth_buffer.stencil_info.format != StencilFormat::Invalid))) {
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const auto htile_address = regs.depth_htile_data_base.GetAddress();
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const auto htile_address = regs.depth_htile_data_base.GetAddress();
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const auto& hint = liverpool->last_db_extent;
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const auto& hint = liverpool->last_db_extent;
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auto& [image_id, desc] =
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auto& [image_id, desc] =
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@ -159,25 +157,29 @@ RenderState Rasterizer::PrepareRenderState(u32 mrt_mask) {
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state.width = std::min<u32>(state.width, image.info.size.width);
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state.width = std::min<u32>(state.width, image.info.size.width);
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state.height = std::min<u32>(state.height, image.info.size.height);
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state.height = std::min<u32>(state.height, image.info.size.height);
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state.has_depth = regs.depth_buffer.DepthValid();
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state.has_stencil = regs.depth_buffer.StencilValid();
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if (state.has_depth) {
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state.depth_attachment = {
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state.depth_attachment = {
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.imageView = *image_view.image_view,
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.imageView = *image_view.image_view,
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.imageLayout = vk::ImageLayout::eUndefined,
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.imageLayout = vk::ImageLayout::eUndefined,
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.loadOp = is_depth_clear ? vk::AttachmentLoadOp::eClear : vk::AttachmentLoadOp::eLoad,
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.loadOp =
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is_depth_clear ? vk::AttachmentLoadOp::eClear : vk::AttachmentLoadOp::eLoad,
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.storeOp = vk::AttachmentStoreOp::eStore,
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.storeOp = vk::AttachmentStoreOp::eStore,
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.clearValue = vk::ClearValue{.depthStencil = {.depth = regs.depth_clear}},
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.clearValue = vk::ClearValue{.depthStencil = {.depth = regs.depth_clear}},
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};
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};
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}
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if (state.has_stencil) {
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state.stencil_attachment = {
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state.stencil_attachment = {
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.imageView = *image_view.image_view,
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.imageView = *image_view.image_view,
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.imageLayout = vk::ImageLayout::eUndefined,
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.imageLayout = vk::ImageLayout::eUndefined,
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.loadOp = is_stencil_clear ? vk::AttachmentLoadOp::eClear : vk::AttachmentLoadOp::eLoad,
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.loadOp =
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is_stencil_clear ? vk::AttachmentLoadOp::eClear : vk::AttachmentLoadOp::eLoad,
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.storeOp = vk::AttachmentStoreOp::eStore,
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.storeOp = vk::AttachmentStoreOp::eStore,
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.clearValue = vk::ClearValue{.depthStencil = {.stencil = regs.stencil_clear}},
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.clearValue = vk::ClearValue{.depthStencil = {.stencil = regs.stencil_clear}},
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};
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};
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}
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texture_cache.TouchMeta(htile_address, slice, false);
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texture_cache.TouchMeta(htile_address, slice, false);
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state.has_depth =
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regs.depth_buffer.z_info.format != AmdGpu::Liverpool::DepthBuffer::ZFormat::Invalid;
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state.has_stencil = regs.depth_buffer.stencil_info.format !=
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AmdGpu::Liverpool::DepthBuffer::StencilFormat::Invalid;
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}
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}
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return state;
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return state;
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@ -815,6 +817,38 @@ void Rasterizer::Resolve() {
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mrt1_range.base.layer = liverpool->regs.color_buffers[1].view.slice_start;
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mrt1_range.base.layer = liverpool->regs.color_buffers[1].view.slice_start;
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mrt1_range.extent.layers = liverpool->regs.color_buffers[1].NumSlices() - mrt1_range.base.layer;
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mrt1_range.extent.layers = liverpool->regs.color_buffers[1].NumSlices() - mrt1_range.base.layer;
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mrt0_image.Transit(vk::ImageLayout::eTransferSrcOptimal, vk::AccessFlagBits2::eTransferRead,
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mrt0_range);
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mrt1_image.Transit(vk::ImageLayout::eTransferDstOptimal, vk::AccessFlagBits2::eTransferWrite,
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mrt1_range);
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if (mrt0_image.info.num_samples == 1) {
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// Vulkan does not allow resolve from a single sample image, so change it to a copy.
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// Note that resolving a single-sampled image doesn't really make sense, but a game might do
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// it.
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vk::ImageCopy region = {
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.srcSubresource =
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{
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.aspectMask = vk::ImageAspectFlagBits::eColor,
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.mipLevel = 0,
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.baseArrayLayer = mrt0_range.base.layer,
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.layerCount = mrt0_range.extent.layers,
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},
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.srcOffset = {0, 0, 0},
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.dstSubresource =
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{
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.aspectMask = vk::ImageAspectFlagBits::eColor,
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.mipLevel = 0,
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.baseArrayLayer = mrt1_range.base.layer,
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.layerCount = mrt1_range.extent.layers,
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},
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.dstOffset = {0, 0, 0},
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.extent = {mrt1_image.info.size.width, mrt1_image.info.size.height, 1},
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};
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cmdbuf.copyImage(mrt0_image.image, vk::ImageLayout::eTransferSrcOptimal, mrt1_image.image,
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vk::ImageLayout::eTransferDstOptimal, region);
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} else {
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vk::ImageResolve region = {
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vk::ImageResolve region = {
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.srcSubresource =
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.srcSubresource =
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{
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{
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@ -834,15 +868,9 @@ void Rasterizer::Resolve() {
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.dstOffset = {0, 0, 0},
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.dstOffset = {0, 0, 0},
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.extent = {mrt1_image.info.size.width, mrt1_image.info.size.height, 1},
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.extent = {mrt1_image.info.size.width, mrt1_image.info.size.height, 1},
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};
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};
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cmdbuf.resolveImage(mrt0_image.image, vk::ImageLayout::eTransferSrcOptimal,
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mrt0_image.Transit(vk::ImageLayout::eTransferSrcOptimal, vk::AccessFlagBits2::eTransferRead,
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mrt1_image.image, vk::ImageLayout::eTransferDstOptimal, region);
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mrt0_range);
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}
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mrt1_image.Transit(vk::ImageLayout::eTransferDstOptimal, vk::AccessFlagBits2::eTransferWrite,
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mrt1_range);
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cmdbuf.resolveImage(mrt0_image.image, vk::ImageLayout::eTransferSrcOptimal, mrt1_image.image,
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vk::ImageLayout::eTransferDstOptimal, region);
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}
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}
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void Rasterizer::InlineData(VAddr address, const void* value, u32 num_bytes, bool is_gds) {
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void Rasterizer::InlineData(VAddr address, const void* value, u32 num_bytes, bool is_gds) {
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@ -998,6 +1026,10 @@ void Rasterizer::UpdateViewportScissorState() {
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enable_offset ? regs.window_offset.window_y_offset : 0);
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enable_offset ? regs.window_offset.window_y_offset : 0);
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for (u32 idx = 0; idx < Liverpool::NumViewports; idx++) {
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for (u32 idx = 0; idx < Liverpool::NumViewports; idx++) {
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if (regs.viewports[idx].xscale == 0) {
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// Scissor and viewport counts should be equal.
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continue;
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}
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auto vp_scsr = scsr;
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auto vp_scsr = scsr;
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if (regs.mode_control.vport_scissor_enable) {
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if (regs.mode_control.vport_scissor_enable) {
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vp_scsr.top_left_x =
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vp_scsr.top_left_x =
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@ -1020,13 +1052,6 @@ void Rasterizer::UpdateViewportScissorState() {
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cmdbuf.setScissor(0, scissors);
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cmdbuf.setScissor(0, scissors);
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}
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}
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void Rasterizer::UpdateDepthStencilState() {
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auto& depth = liverpool->regs.depth_control;
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const auto cmdbuf = scheduler.CommandBuffer();
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cmdbuf.setDepthBoundsTestEnable(depth.depth_bounds_enable);
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}
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void Rasterizer::ScopeMarkerBegin(const std::string_view& str) {
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void Rasterizer::ScopeMarkerBegin(const std::string_view& str) {
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if (Config::nullGpu() || !Config::vkMarkersEnabled()) {
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if (Config::nullGpu() || !Config::vkMarkersEnabled()) {
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return;
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return;
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|
@ -74,7 +74,6 @@ private:
|
||||||
|
|
||||||
void UpdateDynamicState(const GraphicsPipeline& pipeline);
|
void UpdateDynamicState(const GraphicsPipeline& pipeline);
|
||||||
void UpdateViewportScissorState();
|
void UpdateViewportScissorState();
|
||||||
void UpdateDepthStencilState();
|
|
||||||
|
|
||||||
bool FilterDraw();
|
bool FilterDraw();
|
||||||
|
|
||||||
|
|
|
@ -30,7 +30,7 @@ void Scheduler::BeginRendering(const RenderState& new_state) {
|
||||||
is_rendering = true;
|
is_rendering = true;
|
||||||
render_state = new_state;
|
render_state = new_state;
|
||||||
|
|
||||||
const auto witdh =
|
const auto width =
|
||||||
render_state.width != std::numeric_limits<u32>::max() ? render_state.width : 1;
|
render_state.width != std::numeric_limits<u32>::max() ? render_state.width : 1;
|
||||||
const auto height =
|
const auto height =
|
||||||
render_state.height != std::numeric_limits<u32>::max() ? render_state.height : 1;
|
render_state.height != std::numeric_limits<u32>::max() ? render_state.height : 1;
|
||||||
|
@ -39,7 +39,7 @@ void Scheduler::BeginRendering(const RenderState& new_state) {
|
||||||
.renderArea =
|
.renderArea =
|
||||||
{
|
{
|
||||||
.offset = {0, 0},
|
.offset = {0, 0},
|
||||||
.extent = {witdh, height},
|
.extent = {width, height},
|
||||||
},
|
},
|
||||||
.layerCount = 1,
|
.layerCount = 1,
|
||||||
.colorAttachmentCount = render_state.num_color_attachments,
|
.colorAttachmentCount = render_state.num_color_attachments,
|
||||||
|
|
|
@ -266,7 +266,7 @@ ImageInfo::ImageInfo(const AmdGpu::Liverpool::ColorBuffer& buffer,
|
||||||
props.is_tiled = buffer.IsTiled();
|
props.is_tiled = buffer.IsTiled();
|
||||||
tiling_mode = buffer.GetTilingMode();
|
tiling_mode = buffer.GetTilingMode();
|
||||||
pixel_format = LiverpoolToVK::SurfaceFormat(buffer.info.format, buffer.NumFormat());
|
pixel_format = LiverpoolToVK::SurfaceFormat(buffer.info.format, buffer.NumFormat());
|
||||||
num_samples = 1 << buffer.attrib.num_fragments_log2;
|
num_samples = buffer.NumSamples();
|
||||||
num_bits = NumBits(buffer.info.format);
|
num_bits = NumBits(buffer.info.format);
|
||||||
type = vk::ImageType::e2D;
|
type = vk::ImageType::e2D;
|
||||||
size.width = hint.Valid() ? hint.width : buffer.Pitch();
|
size.width = hint.Valid() ? hint.width : buffer.Pitch();
|
||||||
|
@ -289,7 +289,7 @@ ImageInfo::ImageInfo(const AmdGpu::Liverpool::DepthBuffer& buffer, u32 num_slice
|
||||||
props.is_tiled = false;
|
props.is_tiled = false;
|
||||||
pixel_format = LiverpoolToVK::DepthFormat(buffer.z_info.format, buffer.stencil_info.format);
|
pixel_format = LiverpoolToVK::DepthFormat(buffer.z_info.format, buffer.stencil_info.format);
|
||||||
type = vk::ImageType::e2D;
|
type = vk::ImageType::e2D;
|
||||||
num_samples = 1 << buffer.z_info.num_samples; // spec doesn't say it is a log2
|
num_samples = buffer.NumSamples();
|
||||||
num_bits = buffer.NumBits();
|
num_bits = buffer.NumBits();
|
||||||
size.width = hint.Valid() ? hint.width : buffer.Pitch();
|
size.width = hint.Valid() ? hint.width : buffer.Pitch();
|
||||||
size.height = hint.Valid() ? hint.height : buffer.Height();
|
size.height = hint.Valid() ? hint.height : buffer.Height();
|
||||||
|
|
Loading…
Reference in a new issue