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core: Return proper address of eh frame/add more opcodes

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This commit is contained in:
IndecisiveTurtle 2024-12-06 00:46:34 +02:00
parent cc4460164d
commit 032072c172
5 changed files with 28 additions and 5 deletions
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4
src/core/module.cpp
View file

@ -470,8 +470,8 @@ OrbisKernelModuleInfoEx Module::GetModuleInfoEx() const {
.tls_align = tls.align,
.init_proc_addr = base_virtual_addr + dynamic_info.init_virtual_addr,
.fini_proc_addr = base_virtual_addr + dynamic_info.fini_virtual_addr,
.eh_frame_hdr_addr = eh_frame_hdr_addr,
.eh_frame_addr = eh_frame_addr,
.eh_frame_hdr_addr = base_virtual_addr + eh_frame_hdr_addr,
.eh_frame_addr = base_virtual_addr + eh_frame_addr,
.eh_frame_hdr_size = eh_frame_hdr_size,
.eh_frame_size = eh_frame_size,
.segments = info.segments,

2
src/emulator.cpp
View file

@ -266,7 +266,7 @@ void Emulator::Run(const std::filesystem::path& file) {
}
void Emulator::LoadSystemModules(const std::filesystem::path& file, std::string game_serial) {
constexpr std::array<SysModules, 10> ModulesToLoad{
constexpr std::array<SysModules, 14> ModulesToLoad{
{{"libSceNgs2.sprx", &Libraries::Ngs2::RegisterlibSceNgs2},
{"libSceFiber.sprx", &Libraries::Fiber::RegisterlibSceFiber},
{"libSceUlt.sprx", nullptr},

21
src/shader_recompiler/frontend/translate/scalar_alu.cpp
View file

@ -50,6 +50,8 @@ void Translator::EmitScalarAlu(const GcnInst& inst) {
return S_OR_B64(NegateMode::None, false, inst);
case Opcode::S_XOR_B32:
return S_XOR_B32(inst);
case Opcode::S_NOT_B32:
return S_NOT_B32(inst);
case Opcode::S_XOR_B64:
return S_OR_B64(NegateMode::None, true, inst);
case Opcode::S_ANDN2_B32:
@ -94,6 +96,8 @@ void Translator::EmitScalarAlu(const GcnInst& inst) {
return S_BREV_B32(inst);
case Opcode::S_BCNT1_I32_B64:
return S_BCNT1_I32_B64(inst);
case Opcode::S_FF1_I32_B64:
return S_FF1_I32_B64(inst);
case Opcode::S_AND_SAVEEXEC_B64:
return S_SAVEEXEC_B64(NegateMode::None, false, inst);
case Opcode::S_ORN2_SAVEEXEC_B64:
@ -301,6 +305,10 @@ void Translator::S_AND_B64(NegateMode negate, const GcnInst& inst) {
ASSERT_MSG(-s32(operand.code) + SignedConstIntNegMin - 1 == -1,
"SignedConstIntNeg must be -1");
return ir.Imm1(true);
case OperandField::LiteralConst:
ASSERT_MSG(operand.code == 0 || operand.code == std::numeric_limits<u32>::max(),
"Unsupported literal {:#x}", operand.code);
return ir.Imm1(operand.code & 1);
default:
UNREACHABLE();
}
@ -382,6 +390,13 @@ void Translator::S_XOR_B32(const GcnInst& inst) {
ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
}
void Translator::S_NOT_B32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 result{ir.BitwiseNot(src0)};
SetDst(inst.dst[0], result);
ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
}
void Translator::S_LSHL_B32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
@ -560,6 +575,12 @@ void Translator::S_BCNT1_I32_B64(const GcnInst& inst) {
ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
}
void Translator::S_FF1_I32_B64(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 result{ir.Select(ir.IEqual(src0, ir.Imm32(0U)), ir.Imm32(-1), ir.FindILsb(src0))};
SetDst(inst.dst[0], result);
}
void Translator::S_SAVEEXEC_B64(NegateMode negate, bool is_or, const GcnInst& inst) {
// This instruction normally operates on 64-bit data (EXEC, VCC, SGPRs)
// However here we flatten it to 1-bit EXEC and 1-bit VCC. For the destination

2
src/shader_recompiler/frontend/translate/translate.h
View file

@ -96,6 +96,7 @@ public:
void S_MUL_I32(const GcnInst& inst);
void S_BFE_U32(const GcnInst& inst);
void S_ABSDIFF_I32(const GcnInst& inst);
void S_NOT_B32(const GcnInst& inst);
// SOPK
void S_MOVK(const GcnInst& inst);
@ -109,6 +110,7 @@ public:
void S_NOT_B64(const GcnInst& inst);
void S_BREV_B32(const GcnInst& inst);
void S_BCNT1_I32_B64(const GcnInst& inst);
void S_FF1_I32_B64(const GcnInst& inst);
void S_GETPC_B64(u32 pc, const GcnInst& inst);
void S_SAVEEXEC_B64(NegateMode negate, bool is_or, const GcnInst& inst);

4
src/video_core/amdgpu/liverpool.cpp
View file

@ -565,7 +565,7 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
}
case PM4ItOpcode::DmaData: {
const auto* dma_data = reinterpret_cast<const PM4DmaData*>(header);
if (dma_data->dst_addr_lo == 0x3022C) {
if (dma_data->dst_addr_lo == 0x3022C || !rasterizer) {
break;
}
if (dma_data->src_sel == DmaDataSrc::Data && dma_data->dst_sel == DmaDataDst::Gds) {
@ -700,7 +700,7 @@ Liverpool::Task Liverpool::ProcessCompute(std::span<const u32> acb, int vqid) {
}
case PM4ItOpcode::DmaData: {
const auto* dma_data = reinterpret_cast<const PM4DmaData*>(header);
if (dma_data->dst_addr_lo == 0x3022C) {
if (dma_data->dst_addr_lo == 0x3022C || !rasterizer) {
break;
}
if (dma_data->src_sel == DmaDataSrc::Data && dma_data->dst_sel == DmaDataDst::Gds) {