2024-04-29 22:23:28 +00:00
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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2024-05-28 22:28:34 +00:00
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#include "common/assert.h"
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2024-04-29 22:23:28 +00:00
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#include "common/bit_field.h"
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#include "common/types.h"
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#include "video_core/amdgpu/pixel_format.h"
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namespace AmdGpu {
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// Table 8.5 Buffer Resource Descriptor [Sea Islands Series Instruction Set Architecture]
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struct Buffer {
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union {
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BitField<0, 44, u64> base_address;
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BitField<48, 14, u64> stride;
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BitField<62, 1, u64> cache_swizzle;
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BitField<63, 1, u64> swizzle_enable;
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};
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u32 num_records;
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union {
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BitField<0, 3, u32> dst_sel_x;
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BitField<3, 3, u32> dst_sel_y;
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BitField<6, 3, u32> dst_sel_z;
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BitField<9, 3, u32> dst_sel_w;
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BitField<12, 3, NumberFormat> num_format;
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BitField<15, 4, DataFormat> data_format;
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BitField<19, 2, u32> element_size;
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BitField<21, 2, u32> index_stride;
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2024-05-26 12:51:35 +00:00
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BitField<23, 1, u32> add_tid_enable;
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2024-04-29 22:23:28 +00:00
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};
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2024-05-28 22:28:34 +00:00
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u32 GetStride() const noexcept {
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2024-06-13 21:58:57 +00:00
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return stride == 0 ? 1U : stride.Value();
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2024-05-28 22:28:34 +00:00
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}
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u32 GetStrideElements(u32 element_size) const noexcept {
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if (stride == 0) {
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return 1U;
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}
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ASSERT(stride % element_size == 0);
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return stride / element_size;
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}
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u32 GetSize() const noexcept {
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return GetStride() * num_records;
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}
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2024-04-29 22:23:28 +00:00
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};
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2024-05-26 22:07:46 +00:00
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enum class ImageType : u64 {
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Buffer = 0,
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Color1D = 8,
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Color2D = 9,
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Color3D = 10,
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Cube = 11,
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Color1DArray = 12,
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Color2DArray = 13,
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Color2DMsaa = 14,
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Color2DMsaaArray = 15,
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};
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constexpr std::string_view NameOf(ImageType type) {
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switch (type) {
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case ImageType::Buffer:
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return "Buffer";
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case ImageType::Color1D:
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return "Color1D";
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case ImageType::Color2D:
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return "Color2D";
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case ImageType::Color3D:
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return "Color3D";
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case ImageType::Cube:
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return "Cube";
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case ImageType::Color1DArray:
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return "Color1DArray";
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case ImageType::Color2DArray:
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return "Color2DArray";
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case ImageType::Color2DMsaa:
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return "Color2DMsaa";
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case ImageType::Color2DMsaaArray:
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return "Color2DMsaaArray";
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default:
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return "Unknown";
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}
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}
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2024-06-02 20:58:23 +00:00
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enum class TilingMode : u32 {
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Depth_MicroTiled = 0x5u,
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Display_Linear = 0x8u,
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Display_MacroTiled = 0xAu,
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Texture_MicroTiled = 0xDu,
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};
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2024-06-06 22:11:34 +00:00
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constexpr std::string_view NameOf(TilingMode type) {
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switch (type) {
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case TilingMode::Depth_MicroTiled:
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return "Depth_MicroTiled";
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case TilingMode::Display_Linear:
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return "Display_Linear";
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case TilingMode::Display_MacroTiled:
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return "Display_MacroTiled";
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case TilingMode::Texture_MicroTiled:
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return "Texture_MicroTiled";
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default:
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return "Unknown";
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}
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}
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2024-05-26 22:07:46 +00:00
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struct Image {
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union {
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BitField<0, 38, u64> base_address;
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BitField<40, 12, u64> min_lod;
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BitField<52, 6, u64> data_format;
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BitField<58, 4, u64> num_format;
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BitField<62, 2, u64> mtype;
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};
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union {
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BitField<0, 14, u64> width;
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BitField<14, 14, u64> height;
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BitField<28, 3, u64> perf_modulation;
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BitField<31, 1, u64> interlaced;
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BitField<32, 3, u64> dst_sel_x;
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BitField<35, 3, u64> dst_sel_y;
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BitField<38, 3, u64> dst_sel_z;
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BitField<41, 3, u64> dst_sel_w;
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BitField<44, 4, u64> base_level;
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BitField<48, 4, u64> last_level;
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BitField<52, 5, u64> tiling_index;
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BitField<57, 1, u64> pow2pad;
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BitField<58, 1, u64> mtype2;
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BitField<59, 1, u64> atc;
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BitField<60, 4, ImageType> type;
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};
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2024-06-01 17:25:31 +00:00
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union {
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BitField<0, 13, u64> depth;
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BitField<13, 14, u64> pitch;
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BitField<32, 13, u64> base_array;
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BitField<45, 13, u64> last_array;
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};
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2024-05-26 22:07:46 +00:00
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VAddr Address() const {
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return base_address << 8;
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}
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2024-06-01 17:25:31 +00:00
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u32 Pitch() const {
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2024-06-02 20:58:23 +00:00
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return pitch + 1;
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2024-06-01 17:25:31 +00:00
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}
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u32 NumLayers() const {
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2024-06-07 13:26:43 +00:00
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u32 slices = type == ImageType::Color3D ? 1 : depth.Value() + 1;
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if (type == ImageType::Cube) {
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slices *= 6;
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}
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if (pow2pad) {
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slices = std::bit_ceil(slices);
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}
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return slices;
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2024-06-01 17:25:31 +00:00
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}
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u32 NumLevels() const {
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2024-06-07 13:26:43 +00:00
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if (type == ImageType::Color2DMsaa || type == ImageType::Color2DMsaaArray) {
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return 1;
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}
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2024-06-01 17:25:31 +00:00
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return last_level + 1;
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}
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2024-05-26 22:07:46 +00:00
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DataFormat GetDataFmt() const noexcept {
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return static_cast<DataFormat>(data_format.Value());
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}
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NumberFormat GetNumberFmt() const noexcept {
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return static_cast<NumberFormat>(num_format.Value());
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}
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2024-06-02 20:58:23 +00:00
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[[nodiscard]] TilingMode GetTilingMode() const {
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return static_cast<TilingMode>(tiling_index.Value());
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}
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[[nodiscard]] bool IsTiled() const {
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return GetTilingMode() != TilingMode::Display_Linear;
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}
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[[nodiscard]] size_t GetSizeAligned() const {
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// TODO: Derive this properly from tiling params
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return (width + 1) * (height + 1) * NumComponents(GetDataFmt());
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}
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2024-05-26 22:07:46 +00:00
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};
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// 8.2.7. Image Sampler [RDNA 2 Instruction Set Architecture]
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enum class ClampMode : u64 {
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Wrap = 0,
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Mirror = 1,
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ClampLastTexel = 2,
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MirrorOnceLastTexel = 3,
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ClampHalfBorder = 4,
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MirrorOnceHalfBorder = 5,
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ClampBorder = 6,
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MirrorOnceBorder = 7,
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};
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enum class AnisoRatio : u64 {
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One,
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Two,
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Four,
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Eight,
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Sixteen,
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};
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enum class DepthCompare : u64 {
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Never = 0,
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Less = 1,
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Equal = 2,
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LessEqual = 3,
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Greater = 4,
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NotEqual = 5,
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GreaterEqual = 6,
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Always = 7,
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};
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enum class FilterMode : u64 {
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Blend = 0,
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Min = 1,
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Max = 2,
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};
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enum class Filter : u64 {
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Point = 0,
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Bilinear = 1,
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AnisoPoint = 2,
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AnisoLinear = 3,
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};
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enum class MipFilter : u64 {
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None = 0,
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Point = 1,
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Linear = 2,
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};
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enum class BorderColor : u64 {
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OpaqueBlack = 0,
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TransparentBlack = 1,
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White = 2,
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Custom = 3,
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};
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// Table 8.12 Sampler Resource Definition
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struct Sampler {
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union {
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BitField<0, 3, ClampMode> clamp_x;
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BitField<3, 3, ClampMode> clamp_y;
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BitField<6, 3, ClampMode> clamp_z;
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BitField<9, 3, AnisoRatio> max_aniso;
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BitField<12, 3, DepthCompare> depth_compare_func;
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BitField<15, 1, u64> force_unnormalized;
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BitField<16, 3, u64> aniso_threshold;
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BitField<19, 1, u64> mc_coord_trunc;
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BitField<20, 1, u64> force_degamma;
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BitField<21, 6, u64> aniso_bias;
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BitField<27, 1, u64> trunc_coord;
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BitField<28, 1, u64> disable_cube_wrap;
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BitField<29, 2, FilterMode> filter_mode;
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BitField<32, 12, u64> min_lod;
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BitField<44, 12, u64> max_lod;
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BitField<56, 4, u64> perf_mip;
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BitField<60, 4, u64> perf_z;
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};
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union {
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BitField<0, 14, u64> lod_bias;
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BitField<14, 6, u64> lod_bias_sec;
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BitField<20, 2, Filter> xy_mag_filter;
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BitField<22, 2, Filter> xy_min_filter;
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BitField<24, 2, u64> z_filter;
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BitField<26, 2, MipFilter> mip_filter;
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BitField<28, 1, u64> mip_point_preclamp;
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BitField<29, 1, u64> disable_lsb_ceil;
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BitField<30, 2, u64> unused0;
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BitField<32, 12, u64> border_color_ptr;
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BitField<42, 18, u64> unused1;
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BitField<62, 2, BorderColor> border_color_type;
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};
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float LodBias() const noexcept {
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2024-06-15 11:36:07 +00:00
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return static_cast<float>(static_cast<int16_t>((lod_bias.Value() ^ 0x2000u) - 0x2000u)) /
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256.0f;
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2024-05-26 22:07:46 +00:00
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}
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float MinLod() const noexcept {
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return static_cast<float>(min_lod);
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}
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float MaxLod() const noexcept {
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return static_cast<float>(max_lod);
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}
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};
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2024-04-29 22:23:28 +00:00
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} // namespace AmdGpu
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2024-05-26 22:07:46 +00:00
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template <>
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struct fmt::formatter<AmdGpu::ImageType> {
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constexpr auto parse(format_parse_context& ctx) {
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return ctx.begin();
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}
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auto format(AmdGpu::ImageType type, format_context& ctx) const {
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return fmt::format_to(ctx.out(), "{}", AmdGpu::NameOf(type));
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}
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};
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