mirror of
https://github.com/Ryujinx/Ryujinx.git
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Implement Ssubw_V and Usubw_V instructions. (#287)
* Update AOpCodeTable.cs * Update AInstEmitSimdHelper.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdMove.cs * Update AInstEmitSimdCmp.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs
This commit is contained in:
LDj3SNuD
gdkchan
parent
120fe6b74a
commit
fa5545aab8
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@ -387,6 +387,7 @@ namespace ChocolArm64
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SetA64("0100111101xxxxxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm));
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SetA64("0x00111100>>>xxx000101xxxxxxxxxx", AInstEmit.Ssra_V, typeof(AOpCodeSimdShImm));
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SetA64("0100111101xxxxxx000101xxxxxxxxxx", AInstEmit.Ssra_V, typeof(AOpCodeSimdShImm));
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SetA64("0x001110<<1xxxxx001100xxxxxxxxxx", AInstEmit.Ssubw_V, typeof(AOpCodeSimdReg));
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SetA64("0x00110000000000xxxxxxxxxxxxxxxx", AInstEmit.St__Vms, typeof(AOpCodeSimdMemMs));
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SetA64("0x001100100xxxxxxxxxxxxxxxxxxxxx", AInstEmit.St__Vms, typeof(AOpCodeSimdMemMs));
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SetA64("0x00110100x00000xxxxxxxxxxxxxxxx", AInstEmit.St__Vss, typeof(AOpCodeSimdMemSs));
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@ -430,6 +431,7 @@ namespace ChocolArm64
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SetA64("0110111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_V, typeof(AOpCodeSimdShImm));
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SetA64("0x10111100>>>xxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm));
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SetA64("0110111101xxxxxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm));
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SetA64("0x101110<<1xxxxx001100xxxxxxxxxx", AInstEmit.Usubw_V, typeof(AOpCodeSimdReg));
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SetA64("0>001110<<0xxxxx000110xxxxxxxxxx", AInstEmit.Uzp1_V, typeof(AOpCodeSimdReg));
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SetA64("0>001110<<0xxxxx010110xxxxxxxxxx", AInstEmit.Uzp2_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<100001001010xxxxxxxxxx", AInstEmit.Xtn_V, typeof(AOpCodeSimd));
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@ -1072,6 +1072,11 @@ namespace ChocolArm64.Instruction
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EmitVectorSaturatingNarrowOpSxZx(Context, () => { });
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}
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public static void Ssubw_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Sub));
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}
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public static void Sub_S(AILEmitterCtx Context)
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{
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EmitScalarBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));
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@ -1225,5 +1230,10 @@ namespace ChocolArm64.Instruction
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{
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EmitVectorSaturatingNarrowOpZxZx(Context, () => { });
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}
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public static void Usubw_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));
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}
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}
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}
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@ -364,7 +364,7 @@ namespace ChocolArm64.Instruction
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = (!Scalar ? Bytes >> Op.Size : 1);
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int Elems = !Scalar ? Bytes >> Op.Size : 1;
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ulong SzMask = ulong.MaxValue >> (64 - (8 << Op.Size));
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@ -408,7 +408,7 @@ namespace ChocolArm64.Instruction
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = (!Scalar ? Bytes >> Op.Size : 1);
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int Elems = !Scalar ? Bytes >> Op.Size : 1;
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ulong SzMask = ulong.MaxValue >> (64 - (8 << Op.Size));
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@ -522,4 +522,4 @@ namespace ChocolArm64.Instruction
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Context.MarkLabel(LblEnd);
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}
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}
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}
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}
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@ -419,20 +419,25 @@ namespace ChocolArm64.Instruction
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int SizeF = Op.Size & 1;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> SizeF + 2;
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for (int Index = 0; Index < (Bytes >> SizeF + 2); Index++)
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bool Rd = (Opers & OperFlags.Rd) != 0;
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bool Rn = (Opers & OperFlags.Rn) != 0;
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bool Rm = (Opers & OperFlags.Rm) != 0;
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for (int Index = 0; Index < Elems; Index++)
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{
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if (Opers.HasFlag(OperFlags.Rd))
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if (Rd)
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{
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EmitVectorExtractF(Context, Op.Rd, Index, SizeF);
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}
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if (Opers.HasFlag(OperFlags.Rn))
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if (Rn)
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{
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EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
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}
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if (Opers.HasFlag(OperFlags.Rm))
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if (Rm)
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{
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EmitVectorExtractF(Context, ((AOpCodeSimdReg)Op).Rm, Index, SizeF);
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}
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@ -469,8 +474,9 @@ namespace ChocolArm64.Instruction
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int SizeF = Op.Size & 1;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> SizeF + 2;
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for (int Index = 0; Index < (Bytes >> SizeF + 2); Index++)
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for (int Index = 0; Index < Elems; Index++)
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{
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if (Ternary)
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{
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@ -531,19 +537,23 @@ namespace ChocolArm64.Instruction
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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bool Rd = (Opers & OperFlags.Rd) != 0;
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bool Rn = (Opers & OperFlags.Rn) != 0;
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bool Rm = (Opers & OperFlags.Rm) != 0;
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for (int Index = 0; Index < Elems; Index++)
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{
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if (Opers.HasFlag(OperFlags.Rd))
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if (Rd)
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{
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EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
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}
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if (Opers.HasFlag(OperFlags.Rn))
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if (Rn)
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{
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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}
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if (Opers.HasFlag(OperFlags.Rm))
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if (Rm)
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{
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EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Op.Size, Signed);
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}
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@ -662,9 +672,6 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitStvectmp();
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int Elems = 8 >> Op.Size;
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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@ -707,9 +714,6 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitStvectmp();
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int Elems = 8 >> Op.Size;
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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@ -747,21 +751,25 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Bytes = Op.GetBitsCount() >> 3;
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int Words = Op.GetBitsCount() >> 4;
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int Pairs = Words >> Op.Size;
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int Elems = Bytes >> Op.Size;
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int Half = Elems >> 1;
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for (int Index = 0; Index < Elems; Index++)
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for (int Index = 0; Index < Pairs; Index++)
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{
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int Elem = (Index & (Half - 1)) << 1;
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int Idx = Index << 1;
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EmitVectorExtract(Context, Index < Half ? Op.Rn : Op.Rm, Elem + 0, Op.Size, Signed);
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EmitVectorExtract(Context, Index < Half ? Op.Rn : Op.Rm, Elem + 1, Op.Size, Signed);
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EmitVectorExtract(Context, Op.Rn, Idx, Op.Size, Signed);
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EmitVectorExtract(Context, Op.Rn, Idx + 1, Op.Size, Signed);
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Emit();
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EmitVectorInsertTmp(Context, Index, Op.Size);
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EmitVectorExtract(Context, Op.Rm, Idx, Op.Size, Signed);
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EmitVectorExtract(Context, Op.Rm, Idx + 1, Op.Size, Signed);
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Emit();
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EmitVectorInsertTmp(Context, Pairs + Index, Op.Size);
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EmitVectorInsertTmp(Context, Index, Op.Size);
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}
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Context.EmitLdvectmp();
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@ -818,7 +826,7 @@ namespace ChocolArm64.Instruction
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int Part = !Scalar && (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0;
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long TMaxValue = SignedDst ? (1 << (ESize - 1)) - 1 : (1L << ESize) - 1L;
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long TMaxValue = SignedDst ? (1 << (ESize - 1)) - 1 : (long)(~0UL >> (64 - ESize));
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long TMinValue = SignedDst ? -((1 << (ESize - 1))) : 0;
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Context.EmitLdc_I8(0L);
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@ -871,7 +879,7 @@ namespace ChocolArm64.Instruction
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if (Scalar)
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{
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EmitVectorZeroLower(Context, Op.Rd);
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EmitVectorZeroLowerTmp(Context);
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}
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EmitVectorInsertTmp(Context, Part + Index, Op.Size);
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@ -963,6 +971,11 @@ namespace ChocolArm64.Instruction
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EmitVectorInsert(Context, Rd, 0, 3, 0);
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}
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public static void EmitVectorZeroLowerTmp(AILEmitterCtx Context)
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{
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EmitVectorInsertTmp(Context, 0, 3, 0);
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}
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public static void EmitVectorZeroUpper(AILEmitterCtx Context, int Rd)
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{
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EmitVectorInsert(Context, Rd, 1, 3, 0);
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@ -1008,6 +1021,20 @@ namespace ChocolArm64.Instruction
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Context.EmitStvec(Reg);
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}
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public static void EmitVectorInsertTmp(AILEmitterCtx Context, int Index, int Size, long Value)
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{
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ThrowIfInvalid(Index, Size);
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Context.EmitLdc_I8(Value);
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Context.EmitLdvectmp();
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Context.EmitLdc_I4(Index);
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Context.EmitLdc_I4(Size);
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AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInsertInt));
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Context.EmitStvectmp();
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}
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public static void EmitVectorInsertF(AILEmitterCtx Context, int Reg, int Index, int Size)
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{
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ThrowIfInvalidF(Index, Size);
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@ -295,13 +295,22 @@ namespace ChocolArm64.Instruction
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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if (Part != 0)
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{
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Context.EmitLdvec(Op.Rd);
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Context.EmitStvectmp();
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}
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size + 1);
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EmitVectorInsert(Context, Op.Rd, Part + Index, Op.Size);
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EmitVectorInsertTmp(Context, Part + Index, Op.Size);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Part == 0)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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@ -342,7 +351,7 @@ namespace ChocolArm64.Instruction
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EmitVectorExtractZx(Context, Op.Rm, Idx + Part, Op.Size);
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EmitVectorInsertTmp(Context, Idx + 1, Op.Size);
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EmitVectorInsertTmp(Context, Idx , Op.Size);
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EmitVectorInsertTmp(Context, Idx, Op.Size);
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}
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Context.EmitLdvectmp();
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@ -398,7 +407,7 @@ namespace ChocolArm64.Instruction
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EmitVectorExtractZx(Context, Op.Rm, Base + Index, Op.Size);
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EmitVectorInsertTmp(Context, Idx + 1, Op.Size);
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EmitVectorInsertTmp(Context, Idx , Op.Size);
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EmitVectorInsertTmp(Context, Idx, Op.Size);
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}
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Context.EmitLdvectmp();
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@ -1377,6 +1377,60 @@ namespace Ryujinx.Tests.Cpu
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});
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Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
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}
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[Test, Description("XTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
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public void Xtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S>
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{
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uint Opcode = 0x0E212800; // XTN V0.8B, V0.8H
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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SimdFp.Xtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("XTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
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public void Xtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S>
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{
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uint Opcode = 0x4E212800; // XTN2 V0.16B, V0.8H
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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SimdFp.Xtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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#endif
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}
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}
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@ -1659,6 +1659,130 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[Test, Pairwise, Description("SADDW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
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public void Saddw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[Values(2u, 0u)] uint Rm,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D>
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{
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uint Opcode = 0x0E201000; // SADDW V0.8H, V0.8H, V0.8B
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Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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Vector128<float> V2 = MakeVectorE0(B);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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AArch64.Vpart(2, 0, new Bits(B));
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SimdFp.Saddw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SADDW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
|
||||
public void Saddw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D>
|
||||
{
|
||||
uint Opcode = 0x4E201000; // SADDW2 V0.8H, V0.8H, V0.16B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE1(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 1, new Bits(B));
|
||||
SimdFp.Saddw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SSUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
|
||||
public void Ssubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D>
|
||||
{
|
||||
uint Opcode = 0x0E203000; // SSUBW V0.8H, V0.8H, V0.8B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B));
|
||||
SimdFp.Ssubw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SSUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
|
||||
public void Ssubw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D>
|
||||
{
|
||||
uint Opcode = 0x4E203000; // SSUBW2 V0.8H, V0.8H, V0.16B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE1(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 1, new Bits(B));
|
||||
SimdFp.Ssubw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SUB <V><d>, <V><n>, <V><m>")]
|
||||
public void Sub_S_D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
|
|
@ -2184,6 +2308,130 @@ namespace Ryujinx.Tests.Cpu
|
|||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UADDW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
|
||||
public void Uaddw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D>
|
||||
{
|
||||
uint Opcode = 0x2E201000; // UADDW V0.8H, V0.8H, V0.8B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B));
|
||||
SimdFp.Uaddw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UADDW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
|
||||
public void Uaddw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D>
|
||||
{
|
||||
uint Opcode = 0x6E201000; // UADDW2 V0.8H, V0.8H, V0.16B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE1(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 1, new Bits(B));
|
||||
SimdFp.Uaddw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("USUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
|
||||
public void Usubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D>
|
||||
{
|
||||
uint Opcode = 0x2E203000; // USUBW V0.8H, V0.8H, V0.8B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B));
|
||||
SimdFp.Usubw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("USUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
|
||||
public void Usubw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D>
|
||||
{
|
||||
uint Opcode = 0x6E203000; // USUBW2 V0.8H, V0.8H, V0.16B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE1(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 1, new Bits(B));
|
||||
SimdFp.Usubw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Uzp1_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
|
|
|
|||
|
|
@ -3315,6 +3315,37 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
Vpart(d, part, result);
|
||||
}
|
||||
|
||||
// xtn_advsimd.html
|
||||
public static void Xtn_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = 64;
|
||||
int part = (int)UInt(Q);
|
||||
int elements = datasize / esize;
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(2 * datasize, n);
|
||||
Bits element;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element = Elem(operand, e, 2 * esize);
|
||||
|
||||
Elem(result, e, esize, element[esize - 1, 0]);
|
||||
}
|
||||
|
||||
Vpart(d, part, result);
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region "SimdReg"
|
||||
|
|
@ -4395,8 +4426,8 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
int part = (int)UInt(Q);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
bool accumulate = (op == false);
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
|
@ -4484,8 +4515,8 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
int part = (int)UInt(Q);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
bool accumulate = (op == false);
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
|
@ -4511,6 +4542,108 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
V(d, result);
|
||||
}
|
||||
|
||||
// saddw_advsimd.html
|
||||
public static void Saddw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
const bool o1 = false;
|
||||
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = 64;
|
||||
int part = (int)UInt(Q);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool sub_op = (o1 == true);
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(2 * datasize);
|
||||
Bits operand1 = V(2 * datasize, n);
|
||||
Bits operand2 = Vpart(datasize, m, part);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger sum;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, 2 * esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
if (sub_op)
|
||||
{
|
||||
sum = element1 - element2;
|
||||
}
|
||||
else
|
||||
{
|
||||
sum = element1 + element2;
|
||||
}
|
||||
|
||||
Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// ssubw_advsimd.html
|
||||
public static void Ssubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
const bool o1 = true;
|
||||
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = 64;
|
||||
int part = (int)UInt(Q);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool sub_op = (o1 == true);
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(2 * datasize);
|
||||
Bits operand1 = V(2 * datasize, n);
|
||||
Bits operand2 = Vpart(datasize, m, part);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger sum;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, 2 * esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
if (sub_op)
|
||||
{
|
||||
sum = element1 - element2;
|
||||
}
|
||||
else
|
||||
{
|
||||
sum = element1 + element2;
|
||||
}
|
||||
|
||||
Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sub_advsimd.html#SUB_asisdsame_only
|
||||
public static void Sub_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
|
@ -4785,8 +4918,8 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
int part = (int)UInt(Q);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
bool accumulate = (op == false);
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
|
@ -4874,8 +5007,8 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
int part = (int)UInt(Q);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
bool accumulate = (op == false);
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
|
@ -4901,6 +5034,108 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
V(d, result);
|
||||
}
|
||||
|
||||
// uaddw_advsimd.html
|
||||
public static void Uaddw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
const bool o1 = false;
|
||||
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = 64;
|
||||
int part = (int)UInt(Q);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool sub_op = (o1 == true);
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(2 * datasize);
|
||||
Bits operand1 = V(2 * datasize, n);
|
||||
Bits operand2 = Vpart(datasize, m, part);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger sum;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, 2 * esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
if (sub_op)
|
||||
{
|
||||
sum = element1 - element2;
|
||||
}
|
||||
else
|
||||
{
|
||||
sum = element1 + element2;
|
||||
}
|
||||
|
||||
Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// usubw_advsimd.html
|
||||
public static void Usubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
const bool o1 = true;
|
||||
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = 64;
|
||||
int part = (int)UInt(Q);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool sub_op = (o1 == true);
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(2 * datasize);
|
||||
Bits operand1 = V(2 * datasize, n);
|
||||
Bits operand2 = Vpart(datasize, m, part);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger sum;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, 2 * esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
if (sub_op)
|
||||
{
|
||||
sum = element1 - element2;
|
||||
}
|
||||
else
|
||||
{
|
||||
sum = element1 + element2;
|
||||
}
|
||||
|
||||
Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// uzp1_advsimd.html
|
||||
public static void Uzp1_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue