mirror of
https://github.com/Mr-Wiseguy/N64Recomp.git
synced 2024-12-26 17:36:16 +00:00
Added some missing float comparison instructions and fixed functions incorrectly getting detected as the entrypoint
This commit is contained in:
parent
9a4f650c9b
commit
72fe4ed79c
|
@ -661,7 +661,7 @@ bool read_symbols(RecompPort::Context& context, const ELFIO::elfio& elf_file, EL
|
|||
context.functions_by_vram[vram].push_back(context.functions.size());
|
||||
|
||||
// Find the entrypoint by rom address in case it doesn't have vram as its value
|
||||
if (rom_address == 0x1000 && type == ELFIO::STT_FUNC) {
|
||||
if (has_entrypoint && rom_address == 0x1000 && type == ELFIO::STT_FUNC) {
|
||||
vram = entrypoint;
|
||||
found_entrypoint_func = true;
|
||||
name = "recomp_entrypoint";
|
||||
|
|
|
@ -684,7 +684,11 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::C
|
|||
case InstrId::cpu_c_olt_s:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
//print_line("*(volatile int*)0 = 0;");
|
||||
print_line("c1cs = ctx->f{}.fl < ctx->f{}.fl", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_ult_s:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.fl < ctx->f{}.fl", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_lt_d:
|
||||
|
@ -692,6 +696,16 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::C
|
|||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.d < ctx->f{}.d", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_olt_d:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.d < ctx->f{}.d", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_ult_d:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.d < ctx->f{}.d", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_le_s:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
|
@ -700,13 +714,11 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::C
|
|||
case InstrId::cpu_c_ole_s:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
//print_line("*(volatile int*)0 = 0;");
|
||||
print_line("c1cs = ctx->f{}.fl <= ctx->f{}.fl", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_ule_s:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
//print_line("*(volatile int*)0 = 0;");
|
||||
print_line("c1cs = ctx->f{}.fl <= ctx->f{}.fl", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_le_d:
|
||||
|
@ -714,16 +726,56 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::C
|
|||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.d <= ctx->f{}.d", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_ole_d:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.d <= ctx->f{}.d", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_ule_d:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.d <= ctx->f{}.d", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_eq_s:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.fl == ctx->f{}.fl", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_ueq_s:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.fl == ctx->f{}.fl", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_ngl_s:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.fl == ctx->f{}.fl", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_seq_s:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.fl == ctx->f{}.fl", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_eq_d:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.d == ctx->f{}.d", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_ueq_d:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.d == ctx->f{}.d", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_ngl_d:
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.d == ctx->f{}.d", fs, ft);
|
||||
break;
|
||||
case InstrId::cpu_c_deq_d: // TODO rename to c_seq_d when fixed in rabbitizer
|
||||
print_line("CHECK_FR(ctx, {})", fs);
|
||||
print_line("CHECK_FR(ctx, {})", ft);
|
||||
print_line("c1cs = ctx->f{}.d == ctx->f{}.d", fs, ft);
|
||||
break;
|
||||
|
||||
// Cop1 branches
|
||||
case InstrId::cpu_bc1tl:
|
||||
|
|
Loading…
Reference in a new issue